Document Number: 002-10635 Rev. *I
Page
208 of 325
S6J3310/20/30/40 Series
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
SCK ↑ → SCS ↓
clock switching
time
t
SCC
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCS0x, SCS1x,
SCS2x_1,
SCS3x_1, SCS4,
SCS8x to SCS12x
Master
mode
round
operation
(CL = 20 pF,
I
OL
= -5 mA,
I
OH
= 5 mA)
4t
CLK_LCPnA
*4
+0
4t
CLK_LCPnA
*
4
+15
ns
SCK16 to SCK17
SCS16x to SCS17x
4t
CLK_COMP
+0
4t
CLK_COMP
+15
ns
SCK2_0, SCK3_0,
SCS2x_0, SCS3x_0
Master
mode
round
operation
(CL = 20 pF,
I
OL
= -10 mA,
I
OH
= 10 mA)
4t
CLK_LCPnA
*4
+0
4t
CLK_LCPnA
*
4
+10
ns
*1:
t
CSSU
= SCSTR:CSSU[7:0] x serial chip select timing operating clock
*2:
t
CSHD
= SCSTR:CSHD[7:0] x serial chip select timing operating clock
*3:
t
CSDS
= SCSTR:CSDS[15:0] x serial chip select timing operating clock
For details on
*1
,
*2
, and
*3
above, see the Traveo™ Platform Hardware Manual.
*4 t
CLK_LCPnA
n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:
−
This is the AC characteristic in CLK synchronized mode.
−
CL is the load capacitance applied to pins during testing.
−
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the Traveo™ Platform Hardware Manual.
Master mode
SCK output
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
t
CSSI
SCS output
t
CSHI
t
CSDI
V
OL
V
OL
V
OH
V
OH
V
OH
V
OL
