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Cypress S6J331EJSESE20000, Manual

The Cypress S6J331EJSESE20000 is a cutting-edge microcontroller that offers high performance and versatility for a wide range of applications. Users can easily access the comprehensive user manual for this product for free download at manualshive.com, providing detailed instructions on how to maximize its capabilities.

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Document Number: 002-10635 Rev. *I 

 

Page 

25 of 325

 

 
 

 

S6J3310/20/30/40 Series 

Figure 4-11: TEQFP-144 (S6J333xHyz *1) 

 

*1: x, y, z are selected from the following parameters: 

x: E, D, C, B (Memory Size) 
y: S, A, B, U, C, D, T, E, F, V, G, H (Option) 
z: C, D, E (Revision) 

 

 

 

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-

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L

C

D

D

4

L

C

D

D

3

-

-

L

C

D

D

0

-

-

-

-

-

-

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-

-

-

SC

S4

3

_

0

SC

S4

2

_

0

L

C

D

D

2

L

C

D

D

1

SD

A4

SC

L

4

-

-

SC

S3

2

_

1

SC

S3

1

_

1

-

-

-

SC

S2

3

_

1

-

-

-

-

SC

L

1

2

-

-

-

SD

A1

1

SC

L

1

1

-

-

-

-

SD

A1

0

SC

L

1

0

-

-

-

SD

A9

-

-

-

-

SC

S4

1

_

0

SC

S4

0

_

0

SO

T

4

_

0

SC

K4

_

0

SI

N

4

_

0

SC

S3

3

_

1

EI

N

T

2

0

_

5

EI

N

T

1

9

_

5

-

-

-

PPG

1

4

_

T

O

U

T

0

_

1

-

-

-

SD

A1

2

SC

K1

2

_

0

SI

N

1

2

_

0

SC

S1

1

1

_

0

SC

S1

1

0

_

0

SO

T

1

1

_

0

SC

K1

1

_

0

-

-

SI

N

1

1

_

0

SC

S1

0

0

_

0

SO

T

1

0

_

0

SC

K1

0

_

0

SI

N

1

0

_

0

SC

S9

1

_

0

SC

S9

0

_

0

SO

T

9

_

0

-

-

EI

N

T

3

_

6

EI

N

T

2

_

6

EI

N

T

1

_

6

EI

N

T

0

_

6

EI

N

T

2

3

_

5

EI

N

T

2

2

_

5

EI

N

T

0

_

0

EI

N

T

2

1

_

5

AD

T

R

G

1

_

2

AD

T

R

G

0

_

1

-

-

-

EI

N

T

1

5

_

5

-

-

SC

S1

2

0

_

0

SO

T

1

2

_

0

PPG

1

2

/1

3

/1

4

/1

5

_

T

IN

1

_

0

PPG

1

5

_

T

O

U

T

2

_

0

PPG

1

5

_

T

O

U

T

0

_

0

PPG

1

4

_

T

O

U

T

2

_

0

PPG

1

4

_

T

O

U

T

0

_

0

PPG

1

3

_

T

O

U

T

2

_

0

-

-

PPG

1

3

_

T

O

U

T

0

_

0

PPG

1

2

_

T

O

U

T

2

_

0

PPG

1

2

_

T

O

U

T

0

_

0

PPG

6

/7

/8

/9

/1

0

/1

1

_

T

IN

1

_

0

PPG

1

1

_

T

O

U

T

2

_

0

PPG

1

1

_

T

O

U

T

0

_

0

PPG

1

0

_

T

O

U

T

2

_

0

PPG

1

0

_

T

O

U

T

0

_

0

-

-

SEG

1

8

SEG

1

7

SEG

1

6

SEG

1

5

SEG

1

4

SEG

1

3

SEG

1

2

SEG

1

1

SEG

1

0

SEG

9

-

-

-

SEG

4

-

-

EI

N

T

9

_

5

EI

N

T

7

_

5

EI

N

T

6

_

5

EI

N

T

2

3

_

0

EI

N

T

4

_

5

EI

N

T

3

_

5

EI

N

T

2

_

5

EI

N

T

0

_

5

-

-

EI

N

T

2

2

_

0

EI

N

T

2

2

_

4

EI

N

T

2

1

_

4

EI

N

T

2

0

_

4

EI

N

T

2

1

_

0

EI

N

T

1

8

_

4

EI

N

T

1

7

_

4

EI

N

T

1

5

_

4

-

-

M

AD

0

M

D

AT

A7

M

D

AT

A6

M

D

AT

A5

M

D

AT

A4

M

D

AT

A3

M

D

AT

A2

M

D

AT

A1

M

D

AT

A0

M

C

SX1

-

-

-

M

C

SX0

-

-

PW

M

2

M

5

PW

M

2

P5

PW

M

1

M

5

PW

M

1

P5

PW

M

2

M

4

PW

M

2

P4

PW

M

1

M

4

PW

M

1

P4

-

-

PW

M

2

M

3

PW

M

2

P3

PW

M

1

M

3

PW

M

1

P3

PW

M

2

M

2

PW

M

2

P2

PW

M

1

M

2

PW

M

1

P2

-

-

D

SP0

_

R

6

_

0

D

SP0

_

R

5

_

0

D

SP0

_

R

4

_

0

D

SP0

_

R

3

_

0

D

SP0

_

R

2

_

0

D

SP0

_

R

1

_

0

D

SP0

_

R

0

_

0

D

SP0

_

C

L

K_

0

D

SP0

_

VSYN

C

_

0

D

SP0

_

H

SYN

C

_

0

-

-

-

D

SP0

_

EN

_

0

-

-

AN

6

3

AN

6

2

AN

6

1

AN

6

0

AN

5

9

AN

5

8

AN

5

7

AN

5

6

-

-

AN

5

5

AN

5

4

AN

5

3

AN

5

2

AN

5

1

AN

5

0

AN

4

9

AN

4

7

-

VSS

P2

_

1

9

P2

_

1

8

P2

_

1

7

P2

_

1

6

P2

_

1

5

P2

_

1

4

P2

_

1

3

P2

_

1

2

P2

_

1

1

P2

_

1

0

VC

C

5

3

VSS

VC

C

1

2

P2

_

0

9

D

VC

C

D

VSS

P2

_

0

8

P2

_

0

7

P2

_

0

6

P2

_

0

5

P2

_

0

4

P2

_

0

3

P2

_

0

2

P2

_

0

1

D

VC

C

D

VSS

P2

_

0

0

P1

_

3

1

P1

_

3

0

P1

_

2

9

P1

_

2

8

P1

_

2

7

P1

_

2

6

P1

_

2

5

D

VC

C

-

S

S

S

S

S

S

S

S2

S

S

-

-

-

S

-

-

P

P

P

P

P

P

P

P

-

-

P

P

P

P

P

P

P

P

-

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

 

-

-

-

-

-

-

-

-

-

-

-

-

-

VCC53

-

1

108

-

DVSS

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

LCDD5

EINT0_1

SEG19

MAD1

DSP0_R7_0

P0_00

S

2

107

P

P1_24

AN46

PWM2M1

EINT14_4

PPG9_TOUT2_0

SCK9_0

SCL9

-

-

-

-

-

-

-

-

-

-

-

-

LCDD6

-

-

SIN1_0

EINT1_0

SEG20

MAD2

DSP0_G0_0

P0_01

S

3

106

P

P1_23

AN45

PWM2P1

EINT20_0

PPG9_TOUT0_0

SIN9_0

-

-

-

-

-

-

-

-

-

-

-

-

LCDD7

-

-

SCL1

SCK1_0

EINT4_1

SEG21

MAD3

DSP0_G1_0

P0_02

S

4

105

P

P1_22

AN44

PWM1M1

EINT13_4

PPG8_TOUT2_0

TX6_0

SCS80_0

-

-

-

-

-

-

-

-

-

-

-

-

LCDD8

-

SDA1

SOT1_0

EINT5_1

SEG22

MAD4

DSP0_G2_0

P0_03

S

5

104

P

P1_21

AN43

PWM1P1

EINT19_0

PPG8_TOUT0_0

RX6_0

SOT8_0

SDA8

-

-

-

-

-

-

-

-

-

-

-

LCDD9

-

SIN0_1

SCS10_0

EINT11_1

SEG23

MAD5

DSP0_G3_0

P0_04

S

6

103

P

P1_20

AN42

PWM2M0

EINT12_4

PPG7_TOUT2_0

SCK8_0

SCL8

-

-

-

-

-

-

-

-

-

-

-

LCDD10

-

-

SOT0_1

SCS11_0

EINT13_1

SEG24

MAD6

DSP0_G4_0

P0_05

S

7

102

P

P1_19

AN41

PWM2P0

EINT18_0

PPG7_TOUT0_0

SIN8_0

-

-

-

-

-

-

-

-

-

-

LCDD11

-

-

SCK0_1

SCS12_0

PPG0_TOUT0_1

EINT15_1

SEG25

MAD7

DSP0_G5_0

I2S1_ECLK_0

P0_06

S

8

101

P

P1_18

AN40

PWM1M0

EINT11_4

PPG6_TOUT2_0

TX5_0

SCS171_0

-

-

-

-

-

-

-

-

-

LCDD12

-

-

SCS00_1

SCS13_0

PPG0_TOUT2_1

EINT23_1

SEG26

MAD8

DSP0_G6_0

I2S1_SD_0

P0_07

S

9

100

P

P1_17

AN39

PWM1P0

EINT17_0

PPG6_TOUT0_0

RX5_0

SCS170_0

-

-

-

-

-

-

-

-

-

-

-

LCDD13

-

-

PPG1_TOUT0_1

EINT0_2

SEG27

MAD9

DSP0_G7_0

I2S1_WS_0

P0_08

S

10

99

-

DVCC

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

LCDD14

-

-

SIN17_1

PPG1_TOUT2_1

EINT1_2

SEG28

MAD10

DSP0_B0_0

I2S1_SCK_0

P0_09

S

11

98

-

DVSS

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

LCDD15

-

-

SCS171_1

PPG2_TOUT0_1

EINT5_2

SEG29

MAD11

DSP0_B1_0

-

P0_10

S

12

97

-

AVSS

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

LCDD16

-

PPG2_TOUT2_1

EINT6_2

SEG30

MAD12

DSP0_B2_0

-

P0_11

S

13

96

-

AVRL5

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

LCDD17

-

PPG3_TOUT0_1

EINT7_2

SEG31

MAD13

DSP0_B3_0

-

P0_12

S

14

95

-

AVRH5

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

CS#

-

PPG3_TOUT2_1

EINT8_2

COM0

MAD14

DSP0_B4_0

-

P0_13

S

15

94

-

AVCC5

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VCC53

-

16

93

H

P1_16

ADTRG0_0

-

EINT9_4

SGO4_0

PPG0/1/2/3/4/5_TIN1_0

OCU10_OTD1_0

TOT49_0

SOT17_0

SDA17

WOT

SYSC0_CLK_0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VSS

-

17

92

-

VCC5

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VCC12

-

18

91

-

VSS

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

WR#

-

SCK4_1

EINT17_2

COM1

MOEX

DSP0_B5_0

P0_14

S

19

90

-

VCC12

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

RD#

SCS40_1

EINT18_2

COM2

MWEX

DSP0_B6_0

P0_15

S

20

89

-

VCC12

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SCS41_1

EINT19_2

COM3

MCLK

DSP0_B7_1

P0_16

S

21

88

H

P1_15

AN32

EINT16_0

SGA4_0

PPG5_TOUT2_0

OCU10_OTD0_0

ICU10_IN1_0

TIN49_0

SCK17_0

SCK12_1

SCL17

INDICATOR0_1

-

-

-

-

-

-

-

-

-

SCS43_1

EINT21_2

V0

MDQM0

DSP0_B7_0

RXCLK_0

P0_17

V

22

87

G

P1_14

AN31

EINT15_0

SGO3_0

PPG5_TOUT0_0

OCU9_OTD1_0

ICU10_IN0_0

TOT48_0

TX3_0

SIN17_0

SYSC0_CLK_1

-

-

-

-

-

-

-

-

RS

-

-

EINT22_2

V1

MCSX2

MDC_1

RXER_0

P0_18

V

23

86

-

VSS

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

RES#

-

-

EINT23_2

V2

MCSX3

COL_1

RXDV_0

P0_19

V

24

85

-

C

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

TE

-

-

EINT0_3

V3

MRDY

CRS_1

TXCLK_0

P0_20

U

25

84

O

MODE

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VCC53

-

26

83

D

PSC_1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VSS

-

27

82

N

RSTX

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

AVSS

-

28

81

G

P1_13

AN24

EINT14_0

SGA3_0

OCU9_OTD0_0

TIN48_0

RX3_0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

29

80

L2

JTAG_TMS

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

30

79

L2

JTAG_TCK

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

AVSS

-

31

78

L2

JTAG_TDI

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

AVCC3_DAC

-

32

77

M

JTAG_TDO

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

33

76

L

JTAG_NTRST

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

34

75

K

X0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

AVSS

-

35

74

K

X1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VSS

-

36

73

-

VSS

-

-

-

-

-

-

-

-

-

-

-

-

-

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

-

B

B

B

B

B

-

B

-

-

B

B

B

B

B

-

-

C

C

C

-

-

-

-

G

G

G

G

G

G

H

H

I

R

R

-

VC

C

3

P0
_

2

1

P0
_

2

2

P0
_

2

3

P0
_

2

4

P0
_

2

5

VSS

P0
_

2

6

VSS

VC

C

3

P0
_

2

7

P0
_

2

8

P0
_

2

9

P0
_

3

0

P0
_

3

1

VSS

VC

C

3

P1
_

0

0

P1
_

0

1

P1
_

0

2

VC

C

1

2

VC

C

1

2

VSS

VC

C

5

P1
_

0

3

P1
_

0

4

P1
_

0

5

P1
_

0

6

P1
_

0

7

P1
_

0

8

P1
_

0

9

P1
_

1

0

N

M

IX

X0
A

X1
A

VC

C

5

-

M

_

SD

AT
A0
_

0

M

_

SD

AT
A0
_

2

M

_

SD

AT
A0
_

1

M

_

SSEL

0

M

_

SD

AT
A0
_

3

-

M

_

SC

L

K0

-

-

M

_

SD

AT
A1
_

0

M

_

SD

AT
A1
_

2

M

_

SD

AT
A1
_

1

M

_

SSEL

1

M

_

SD

AT
A1
_

3

-

-

M

L

BC

L

K

M

L

BSI

G

M

L

BD

AT

-

-

-

-

AN

8

AN

9

AN

1

2

AN

1

3

AN

1

6

AN

1

7

AN

1

8

AN

2

1

-

P1
_

1

1

P1
_

1

2

-

-

M

_

D

Q

3

M

_

D

Q

2

M

_

D

Q

1

M

_

D

Q

0

M

_

C

S#
_

1

-

M

_

C

K

-

-

M

_

R

W
D

S

M

_

D

Q

4

M

_

D

Q

5

M

_

D

Q

6

M

_

D

Q

7

-

-

M

_

C

S#
_

2

C

O

L

_

0

C

R

S_
0

-

-

-

-

EI
N

T

4

_

0

EI
N

T

5

_

0

EI
N

T

6

_

0

EI
N

T

7

_

0

EI
N

T

8

_

0

AD

T

R

G

1

_

1

EI
N

T

1

0

_

0

EI
N

T

1

1

_

0

-

EI
N

T

1

2

_

0

EI
N

T

1

3

_

0

-

-

T

XEN

_

0

T

XD

0

_

0

T

XD

1

_

0

T

XD

2

_

0

T

XD

3

_

0

-

T

XER

_

0

-

-

R

XD

0

_

0

R

XD

1

_

0

R

XD

2

_

0

R

XD

3

_

0

M

D

IO

_

0

-

-

M

D

C

_

0

EI
N

T

1

1

_

3

EI
N

T

1

2

_

3

-

-

-

-

-

-

-

-

-

EI
N

T

9

_

0

-

-

-

PPG

4

_

T

O

U

T

0

_

0

PPG

4

_

T

O

U

T

2

_

0

-

-

EI
N

T

2

_

0

EI
N

T

1

_

3

EI
N

T

2

_

3

EI
N

T

3

_

3

EI
N

T

4

_

3

-

EI
N

T

5

_

3

-

-

EI
N

T

6

_

3

EI
N

T

3

_

0

EI
N

T

7

_

3

EI
N

T

8

_

3

EI
N

T

9

_

3

-

-

EI
N

T

1

0

_

3

SC

S3
2

_

0

SC

S3
3

_

0

-

-

-

-

PPG

0

_

T

O

U

T

0

_

0

PPG

0

_

T

O

U

T

2

_

0

SG

A0
_

0

SG

O

0

_

0

SG

A1
_

0

-

SG

A2
_

0

SG

O

2

_

0

-

O

C

U

8

_

O

T

D

0

_

0

O

C

U

8

_

O

T

D

1

_

0

-

-

SI
N

2

_

0

SC

K2
_

0

SO

T

2

_

0

SC

S2
0

_

0

SC

S2
1

_

0

-

SC

S2
2

_

0

-

-

SC

S2
3

_

0

SI
N

3

_

0

SC

K3
_

0

SO

T

3

_

0

SC

S3
0

_

0

-

-

SC

S3
1

_

0

-

-

-

-

-

-

O

C

U

0

_

O

T

D

0

_

0

O

C

U

0

_

O

T

D

1

_

0

PPG

1

_

T

O

U

T

0

_

0

PPG

1

_

T

O

U

T

2

_

0

PPG

2

_

T

O

U

T

0

_

0

SG

O

1

_

0

PPG

3

_

T

O

U

T

0

_

0

PPG

3

_

T

O

U

T

2

_

0

-

IC

U

9

_

IN

0

_

0

IC

U

9

_

IN

1

_

0

-

-

SI
N

9

_

2

SO

T

9

_

2

SC

K9
_

2

SC

S9
0

_

2

SC

S9
1

_

2

-

-

-

-

SI
N

8

_

2

SC

K8
_

2

SO

T

8

_

2

SC

S8
0

_

2

-

-

-

-

-

-

-

-

-

-

IC

U

0

_

IN

0

_

0

IC

U

0

_

IN

1

_

0

IC

U

1

_

IN

0

_

0

IC

U

1

_

IN

1

_

0

O

C

U

1

_

O

T

D

0

_

0

PPG

2

_

T

O

U

T

2

_

0

O

C

U

2

_

O

T

D

0

_

0

O

C

U

2

_

O

T

D

1

_

0

-

T

IN

1

7

_

0

T

O

T

1

7

_

0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

AI
N

8

BI
N

8

Z

IN

8

AI
N

9

IC

U

2

_

IN

0

_

0

O

C

U

1

_

O

T

D

1

_

0

IC

U

8

_

IN

0

_

0

IC

U

8

_

IN

1

_

0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

T

IN

0

_

0

T

O

T

0

_

0

T

IN

1

_

0

T

O

T

1

_

0

BI
N

9

IC

U

2

_

IN

1

_

0

SC

K1
6

_

0

SO

T

1

6

_

0

-

SC

S1
6

0

_

0

SC

S1
6

1

_

0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

F

R

T

0

/1

/2

/3

_

T

EXT

F

R

T

4

/8

/9

/1

0

_

T

EXT

R

X0
_

0

T

X0
_

0

T

IN

1

6

_

0

Z

IN

9

SC

L

1

6

SD

A1
6

-

IN

D

IC

AT
O

R

0

_

0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SI
N

0

_

0

SC

K0
_

0

SO

T

0

_

0

SC

S0
0

_

0

-

T

O

T

1

6

_

0

T

R

AC

E_
C

T

L

_

0

T

R

AC

E_
C

L

K_
0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SC

L

0

SD

A0

T

R

AC

E1
_

0

T

R

AC

E2
_

0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

T

R

AC

E0
_

0

-

-

SI
N

1

6

_

0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

T

R

AC

E3
_

0

-

-

-

-

-

-

●

TOP VIEW

TEQFP-144

Summary of Contents for S6J331EJSESE20000

Page 1: ...re at up to 240 MHz General purpose I O port up to 148 12 bit A D converter up to 48 channels External interrupt up to 24 channels Base timer up to 32 channels 32 bit reload timer up to 6 channels 32...

Page 2: ...1 I O Circuit Type 31 5 2 Note 36 6 Port Description 37 6 1 Port Description List 37 6 2 Remark 58 7 Port Configuration 59 7 1 Resource Input Configuration Module 59 7 2 Port Output Function Configur...

Page 3: ...ation of S6J3300 series are described Software engineer 002 10185 TraveoTM Platform Hardware Manual 32 Bit Microcontroller Traveo Family S6J33xx S6J34xx S6J35xx Series Hardware Manual Platform Part Th...

Page 4: ...16 Kbyte Instruction cache 16 Kbyte Program FLASH Option See 2 2 1 Work FLASH 112 Kbyte TCRAM 128 Kbyte System SRAM 384 Kbyte Backup RAM 32 Kbyte Security SHE Option Low latency interrupt Available Po...

Page 5: ...ation on 9 1 4 17 Multi function serial interface 12 ch CAN FD 6 ch CAN FD RAM ECC supported 16 KB ch It equivalents to 128 message buffer per channel of MCAN module Ethernet AVB 1 unit No See 2 2 1 M...

Page 6: ...K_CEER VCC DVCC S 5V A B 3V U 5V C D 3V T 5V E F 3V V 5V G H 3V Digit Pin Count H 144pin J 176pin K 208pin Program Work Main Backup E 4 160KB 112KB 512KB 16 16KB D 3 136KB 112KB 512KB 16 16KB C 2 112K...

Page 7: ...2 Pin Restriction Function TEQFP176 TEQFP144 Analog input port 12bit ADC AN4 7 AN10 11 AN14 15 AN25 26 AN28 30 SEG port of LCD controller SEG0 3 SEG5 8 General Purpose I O P4_00 P4_31 P4_00 P4_31 P3_...

Page 8: ...EINT2_2 EINT2_4 EINT3_1 EINT3_2 EINT3_4 EINT4_2 EINT4_4 EINT5_4 EINT5_5 EINT6_1 EINT6_4 EINT7_1 EINT7_4 EINT8_1 EINT8_4 EINT8_5 EINT9_1 EINT9_2 EINT10_1 EINT10_2 EINT10_4 EINT10_5 EINT11_2 EINT11_5 E...

Page 9: ...l in detail Standard 5 pin JTAG interface 4 kB Embedded Trace Buffer 4 bit trace support for TEQFP package System Control See the TraveoTM Platform Hardware Manual in detail Main and sub oscillator is...

Page 10: ...re Hyper BUS DDR HSSPI Product supports down spread and center spread modes with the conditions defined in 9 1 4 3 Internal Clock Timing S6J3310 External Interrupts See the TraveoTM Platform Hardware...

Page 11: ...ltage is supported LVD for internal voltage is supported See 9 1 4 11 and 9 1 4 12 Low voltage detection for RAM retention RVD RVD for RAM retention is effective during the standby mode only That is i...

Page 12: ...veoTM Platform Hardware Manual in detail A unit consists of a pair of 16 bit base timers 16 units that is 32 channels of base timers are available Reload Timer See the TraveoTM Platform Hardware Manua...

Page 13: ...etail Source Clock Timer See the TraveoTM Platform Hardware Manual in detail Graphics Subsystem 80 MHz maximum clock frequency Variable setting about GDC clock Asynchronous with CPU clock 480 x 272 pi...

Page 14: ...nterface Additional Low Latency TX FIFO Interface for DMA configurations MAC Transmit Block half duplex collision back_pressure MAC Filtering Block external address match Wakeup On Lan Energy Efficien...

Page 15: ...P4_20 EINT7_4 SOT16_1 CS ARH0_AIC0_dbg_select PPG3_TOUT2_1 EINT8_2 COM0 MAD14 DSP0_B4_0 I2S0_SCK_0 P0_13 S 21 136 G P4_19 EINT16_1 SIN16_1 VCC53 22 135 VCC5 VSS 23 134 VSS VCC12 24 133 VCC12 SIN1_1 PP...

Page 16: ...C12 24 133 VCC12 SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 TXD1_1 P3_00 T 25 132 VCC12 SCK1_1 PPG4_TOUT2_1 EINT9_2 MAD16 TXD2_1 P3_01 T 26 131 G P4_18 EINT6_4 SIN12_1 SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD3_1...

Page 17: ...VCC12 24 133 VCC12 SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 TXD1_1 P3_00 T 25 132 VCC12 SCK1_1 PPG4_TOUT2_1 EINT9_2 MAD16 TXD2_1 P3_01 T 26 131 G P4_18 EINT6_4 SIN12_1 SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD...

Page 18: ...M0 MAD14 DSP0_B4_0 P0_13 S 21 136 G P4_19 EINT16_1 SIN16_1 VCC53 22 135 VCC5 VSS 23 134 VSS VCC12 24 133 VCC12 SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 P3_00 T 25 132 VCC12 SCK1_1 PPG4_TOUT2_1 EINT9_2 MAD16...

Page 19: ...VSS 17 116 VCC5 VCC12 18 115 VSS SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 TXD1_1 P3_00 T 19 114 VCC12 SCK1_1 PPG4_TOUT2_1 EINT9_2 MAD16 TXD2_1 P3_01 T 20 113 VCC12 SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD3_1 P...

Page 20: ...9_2 MAD16 TXD2_1 P3_01 T 20 113 VCC12 SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD3_1 P3_02 T 21 112 H P1_15 AN32 EINT16_0 SGA4_0 PPG5_TOUT2_0 OCU10_OTD0_0 ICU10_IN1_0 TIN49_0 SCK17_0 SCK12_1 SCL17 INDICATO...

Page 21: ...INT9_2 MAD16 TXD2_1 P3_01 T 20 113 VCC12 SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 TXD3_1 P3_02 T 21 112 H P1_15 AN32 EINT16_0 SGA4_0 PPG5_TOUT2_0 OCU10_OTD0_0 ICU10_IN1_0 TIN49_0 SCK17_0 SCK12_1 SCL17 INDIC...

Page 22: ...VCC5 VCC12 18 115 VSS SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 P3_00 T 19 114 VCC12 SCK1_1 PPG4_TOUT2_1 EINT9_2 MAD16 P3_01 T 20 113 VCC12 SOT1_1 PPG5_TOUT0_1 EINT10_2 MAD17 P3_02 T 21 112 H P1_15 AN32 EINT...

Page 23: ..._0 I2S1_SCK_0 P0_09 S 11 98 DVSS LCDD15 ARH0_AIC0_DNDATA1 ARH0_AIC0_TDA1 SCS171_1 PPG2_TOUT0_1 EINT5_2 SEG29 MAD11 DSP0_B1_0 I2S0_ECLK_0 P0_10 S 12 97 AVSS LCDD16 ARH0_AIC0_dbg_out_1 PPG2_TOUT2_1 EINT...

Page 24: ...98 DVSS LCDD15 SCS171_1 PPG2_TOUT0_1 EINT5_2 SEG29 MAD11 DSP0_B1_0 I2S0_ECLK_0 P0_10 S 12 97 AVSS LCDD16 PPG2_TOUT2_1 EINT6_2 SEG30 MAD12 DSP0_B2_0 I2S0_SD_0 P0_11 S 13 96 AVRL5 LCDD17 PPG3_TOUT0_1 EI...

Page 25: ...1 PPG1_TOUT2_1 EINT1_2 SEG28 MAD10 DSP0_B0_0 I2S1_SCK_0 P0_09 S 11 98 DVSS LCDD15 SCS171_1 PPG2_TOUT0_1 EINT5_2 SEG29 MAD11 DSP0_B1_0 P0_10 S 12 97 AVSS LCDD16 PPG2_TOUT2_1 EINT6_2 SEG30 MAD12 DSP0_B2...

Page 26: ...G1_TOUT0_1 EINT0_2 SEG27 MAD9 DSP0_G7_0 I2S1_WS_0 P0_08 S 10 99 DVCC LCDD14 SIN17_1 PPG1_TOUT2_1 EINT1_2 SEG28 MAD10 DSP0_B0_0 I2S1_SCK_0 P0_09 S 11 98 DVSS LCDD15 SCS171_1 PPG2_TOUT0_1 EINT5_2 SEG29...

Page 27: ...ING PLANE A A b 0 08 C A B D 8 SIDE VIEW TOP VIEW BOTTOM VIEW b SECTION A A c 10 L1 L R1 R2 GAUGE PLANE DETAIL A L2 E1 EXPOSED PAD L 1 1 00 REF L c 0 45 0 09 0 60 0 75 0 20 NOM MIN 28 00 BSC D1 R 2 E...

Page 28: ...00 BSC D A 1 A 26 00 BSC 0 05 SYMBOL MAX 8 0 20 1 70 0 15 D2 D3 E 2 E 3 6 65 REF 5 45 REF 6 65 REF 5 45 REF b 0 17 0 22 0 27 e 0 50 BSC DIMENSION 1 R 0 08 L 2 0 25 EXPOSED PAD D1 D 4 5 7 E1 E 0 20 C...

Page 29: ...BSC 22 00 BSC D A 1 A 22 00 BSC 0 05 SYMBOL MAX 8 0 20 1 70 0 15 D2 D3 E 2 E 3 5 80 REF 4 60 REF 5 80 REF 4 60 REF b 0 17 0 22 0 27 e 0 50 BSC DIMENSION 1 R 0 08 L 2 0 25 D1 D 4 5 7 E1 E 0 20 C A B D...

Page 30: ...ION 1 R L 2 0 25 18 00 BSC 16 00 BSC 5 80 REF 4 60 REF 18 00 BSC 16 00 BSC 5 80 REF 4 60 REF 0 08 0 08 0 20 0 09 0 20 0 13 0 18 0 23 0 45 0 60 0 75 1 00 REF 0 40 BSC D1 D 4 5 7 E1 E 0 20 C A B D 0 20...

Page 31: ...wn resistor control CMOS hysteresis input MediaLB level hysteresis input D External 1 2 V regulator control Output 2 mA E General purpose I O port Output 1 mA 2 mA or 5 mA selectable 50 k with pull up...

Page 32: ...le 50 k with pull up resistor control 50 k with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input I 50 k with pull up CMOS hysteresis input K Main oscillation I O...

Page 33: ...ll down resistor control CMOS hysteresis input Automotive hysteresis input Q General purpose I O port Output 1 mA 2 mA 5 mA or 30 mA selectable 50 k with pull up resistor control 50 k with pull down r...

Page 34: ...ectable 50 k with pull up resistor control 50 k with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input PSS OSC control OSC input Pull up control Digital output Dig...

Page 35: ...utomotive hysteresis input TTL input U General purpose input port with LCDC reference voltage input 50 k with pull up resistor control 50 k with pull down resistor control CMOS hysteresis input Automo...

Page 36: ...up resistor control 50 k with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input 5 2 Note Alphabet which shows I O circuit type is described with corresponding pin...

Page 37: ...26 133 1 16 34 161 1 22 42 193 VSS GND 17 27 36 43 45 52 59 73 86 91 132 144 17 35 44 51 53 60 67 89 104 115 160 176 23 43 52 59 61 68 75 105 121 134 192 208 AVCC3_DAC Audio DAC power supply pin 32 4...

Page 38: ...ace control 1 79 91 ADTRG0_0 A D converter external trigger input pin 0 93 117 139 ADTRG1_0 A D converter external trigger input pin 0 140 ADTRG0_1 A D converter external trigger input pin 1 134 166 1...

Page 39: ...48 177 AN61 ADC Unit1 ch 61 input pin 125 149 178 AN62 ADC Unit1 ch 62 input pin 126 150 179 AN63 ADC Unit1 ch 63 input pin 127 151 181 TX0_0 CAN transmission data 0 output pin 0 64 78 90 TX1_0 CAN tr...

Page 40: ...put pin 0 88 112 129 EINT17_0 External interrupt input pin 0 100 124 148 EINT18_0 External interrupt input pin 0 102 126 150 EINT19_0 External interrupt input pin 0 104 128 152 EINT20_0 External inter...

Page 41: ...NT18_2 External interrupt input pin 2 20 27 35 EINT19_2 External interrupt input pin 2 21 28 36 EINT20_2 External interrupt input pin 2 29 37 EINT21_2 External interrupt input pin 2 22 30 38 EINT22_2...

Page 42: ...al interrupt input pin 4 163 EINT20_4 External interrupt input pin 4 114 138 164 EINT21_4 External interrupt input pin 4 115 139 165 EINT22_4 External interrupt input pin 4 116 140 166 EINT23_4 Extern...

Page 43: ...105 129 153 SCS90_0 Multi function serial ch 9 chip select 0 I O pin 0 111 135 160 SCS91_0 Multi function serial ch 9 chip select 1 output pin 0 112 136 161 SCS100_0 Multi function serial ch 10 chip...

Page 44: ...n serial ch 11 clock I O pin 0 120 144 171 SCK12_0 Multi function serial ch 12 clock I O pin 0 125 149 178 SCK16_0 Multi function serial ch 16 clock I O pin 0 67 83 95 SCK17_0 Multi function serial ch...

Page 45: ...ti function serial ch 9 serial data output pin 0 110 134 158 SOT10_0 Multi function serial ch 10 serial data output pin 0 115 139 165 SOT11_0 Multi function serial ch 11 serial data output pin 0 121 1...

Page 46: ...112 129 PPG6_TOUT0_0 Base timer 12 output pin 0 100 124 148 PPG6_TOUT2_0 Base timer 13 output pin 0 101 125 149 PPG7_TOUT0_0 Base timer 14 output pin 0 102 126 150 PPG7_TOUT2_0 Base timer 15 output pi...

Page 47: ...157 189 PPG14_TOUT0_1 Base timer 28 output pin 1 130 158 190 PPG14_TOUT2_1 Base timer 29 output pin 1 162 194 PPG15_TOUT0_1 Base timer 30 output pin 1 163 195 PPG15_TOUT2_1 Base timer 31 output pin 1...

Page 48: ...tput pin 1 71 83 OCU1_OTD1_1 Output compare 1 ch 1 output pin 1 72 84 OCU2_OTD0_1 Output compare 2 ch 0 output pin 1 75 87 OCU2_OTD1_1 Output compare 2 ch 1 output pin 1 76 88 OCU8_OTD0_1 Output compa...

Page 49: ...ound generator ch 4 SGO output pin 0 93 117 139 SGO0_1 Sound generator ch 0 SGO output pin 1 70 82 SGO1_1 Sound generator ch 1 SGO output pin 1 72 84 SGO2_1 Sound generator ch 2 SGO output pin 1 76 88...

Page 50: ...1 output pin 0 64 78 90 TOT16_0 Reload timer ch 16 output pin 0 66 82 94 TOT17_0 Reload timer ch 17 output pin 0 71 87 103 TOT48_0 Reload timer ch 48 output pin 0 87 111 128 TOT49_0 Reload timer ch 4...

Page 51: ..._0 MCU HS SPI0 data 0 I O pin 38 46 54 M_SDATA0_1 MCU HS SPI0 data 1 I O pin 40 48 56 M_SDATA0_2 MCU HS SPI0 data 2 I O pin 39 47 55 M_SDATA0_3 MCU HS SPI0 data 3 I O pin 42 50 58 M_SDATA1_0 MCU HS SP...

Page 52: ...t Pin 3 3 3 SEG21 LCDC Segment Duty Output Pin 4 4 4 SEG22 LCDC Segment Duty Output Pin 5 5 5 SEG23 LCDC Segment Duty Static Output Pin 6 6 9 SEG24 LCDC Segment Duty Static Output Pin 7 7 10 SEG25 LCD...

Page 53: ...0 LCD Bus IF Data I O pin 139 171 203 LCDD1 LCD Bus IF Data I O pin 140 172 204 LCDD2 LCD Bus IF Data I O pin 141 173 205 LCDD3 LCD Bus IF Data I O pin 142 174 206 LCDD4 LCD Bus IF Data I O pin 143 17...

Page 54: ...input pin 10 10 13 ARH0_AIC1_UPDATA1 APIX input pin 9 9 12 ARH0_AIC1_dbg_out_0 APIX output pin 6 6 9 ARH0_AIC1_dbg_out_1 APIX output pin 5 5 5 ARH0_AIC1_dbg_select APIX input pin 19 26 34 INDICATOR0_0...

Page 55: ...DQM1 External Bus pin 29 37 MCSX0 External Bus pin 130 158 190 MCSX1 External Bus pin 134 166 198 MCSX2 External Bus pin 23 31 39 MCSX3 External Bus pin 24 32 40 MRDY External Bus pin 25 33 41 P0_00 G...

Page 56: ...11 General Purpose I O port 70 86 102 P1_12 General Purpose I O port 71 87 103 P1_13 General Purpose I O port 81 97 113 P1_14 General Purpose I O port 87 111 128 P1_15 General Purpose I O port 88 112...

Page 57: ...32 P3_06 General Purpose I O port 25 33 P3_07 General Purpose I O port 29 37 P3_08 General Purpose I O port 69 81 P3_09 General Purpose I O port 70 82 P3_10 General Purpose I O port 71 83 P3_11 Genera...

Page 58: ...ort 116 P4_17 General Purpose I O port 130 P4_18 General Purpose I O port 131 P4_19 General Purpose I O port 136 P4_20 General Purpose I O port 137 P4_21 General Purpose I O port 138 P4_22 General Pur...

Page 59: ...are available through only one port does not have the multiplexer implemented i e No RIC_RESIN register 7 1 1 RIC S6J3310 Register Offset Resource RESSEL 3 0 PORT SEL 3 0 Source for Resource Input 0 1...

Page 60: ...T49 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN005 0x000A SCS16 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_11 P4_23 PORTSE L 8 15 RIC_RE SIN007 0x000E SIN17 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_14...

Page 61: ...er disable 80 ns noise filter enable RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN011 0x0016 MFS17_T RIGGER RESSEL 0 7 TOT48 TOT49 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN012 0x0018 SCS17...

Page 62: ...ise filter enable RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN024 0x0030 SDA0 RESSEL 0 7 80 ns noise filter disable 80 ns noise filter enable RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN025...

Page 63: ...1 PORTSE L 8 15 RIC_RE SIN030 0x003C SCL1 RESSEL 0 7 80 ns noise filter disable 80 ns noise filter enable RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN031 0x003E SDA1 RESSEL 0 7 80 ns noise filter...

Page 64: ...12 13 14 15 RIC_RE SIN035 0x0046 SIN2 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P0_21 P4_30 PORTSE L 8 15 RIC_RE SIN036 0x0048 SCK2 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P0_22 P4_31 PORTSE L 8 15 RIC_RE SIN0...

Page 65: ...L 0 7 RESSEL 8 15 PORTSE L 0 7 P0_28 P3_28 PORTSE L 8 15 RIC_RE SIN043 0x0056 SCK3 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P0_29 P3_29 PORTSE L 8 15 RIC_RE SIN046 0x005C MFS3_TR IGGER RESSEL 0 7 TOT0 TOT1...

Page 66: ...4 PORTSE L 8 15 RIC_RE SIN051 0x0066 SCL4 RESSEL 0 7 80 ns noise filter disable 80 ns noise filter enable RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN052 0x0068 SDA4 RESSEL 0 7 80 ns noise filter...

Page 67: ...PORTSE L 8 15 RIC_RE SIN078 0x009C SCK8 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_20 P3_09 P0_28 PORTSE L 8 15 RIC_RE SIN079 0x009E SCL8 RESSEL 0 7 80 ns noise filter disable 80 ns noise filter enable R...

Page 68: ...0 PORTSE L 8 15 RIC_RE SIN084 0x00A8 SIN9 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_23 P3_18 P0_21 PORTSE L 8 15 RIC_RE SIN085 0x00AA SCK9 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_24 P3_19 P0_23 PORTSE L 8...

Page 69: ...RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN089 0x00B2 SCS9 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_26 P3_21 P0_24 PORTSE L 8 15 RIC_RE SIN091 0x00B6 SIN10 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_...

Page 70: ...EL 0 7 80 ns noise filter disable 80 ns noise filter enable RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN095 0x00BE MFS10_T RIGGER RESSEL 0 7 TOT16 TOT17 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC...

Page 71: ...filter enable RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN102 0x00CC MFS11_T RIGGER RESSEL 0 7 TOT16 TOT17 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN105 0x00D2 SIN12 RESSEL 0 7 RESSEL 8 1...

Page 72: ...r enable RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN109 0x00DA MFS12_T RIGGER RESSEL 0 7 TOT16 TOT17 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN110 0x00DC SCS12 RESSEL 0 7 RESSEL 8 15 PORT...

Page 73: ...MCAN0 _PIN_A ND_TX RESSEL 8 15 PORTSE L 0 7 P1_05 P3_09 P4_00 PORTSE L 8 15 RIC_RE SIN137 0x0112 RX1 RESSEL 0 7 PORT_ PIN MCAN1 _PIN_A ND_TX RESSEL 8 15 PORTSE L 0 7 P1_07 P3_11 PORTSE L 8 15 RIC_RE S...

Page 74: ...RIC_RE SIN142 0x011C TIN49 RESSEL 0 7 PORT_ PIN TOT48 RLT48_ UFSET RESSEL 8 15 PORTSE L 0 7 P1_15 P3_20 PORTSE L 8 15 RIC_RE SIN144 0x0120 TIN0 RESSEL 0 7 PORT_ PIN TOT1 RLT1_U FSET PPG0_T OUT0 RESSEL...

Page 75: ...3_14 PORTSE L 8 15 RIC_RE SIN192 0x0180 EINT0 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P2_13 P0_00 P0_08 P0_20 P3_17 P2_01 P2_16 PORTSE L 8 15 RIC_RE SIN193 0x0182 EINT1 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7...

Page 76: ...23 P2_04 PORTSE L 8 15 RIC_RE SIN197 0x018A EINT5 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_04 P0_03 P0_10 P0_26 P4_17 P4_28 PORTSE L 8 15 RIC_RE SIN198 0x018C EINT6 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P...

Page 77: ...P2_08 PORTSE L 8 15 RIC_RE SIN202 0x0194 EINT10 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_09 P4_02 P3_02 P1_00 P4_23 P4_31 PORTSE L 8 15 RIC_RE SIN203 0x0196 EINT11 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P...

Page 78: ...P3_27 PORTSE L 8 15 RIC_RE SIN207 0x019E EINT15 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_14 P0_06 P3_05 P4_10 P1_25 P2_09 PORTSE L 8 15 RIC_RE SIN208 0x01A0 EINT16 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P...

Page 79: ...P2_10 PORTSE L 8 15 RIC_RE SIN212 0x01A8 EINT20 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_23 P3_18 P3_07 P4_12 P1_29 P2_11 PORTSE L 8 15 RIC_RE SIN213 0x01AA EINT21 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P...

Page 80: ...5 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN217 0x01B2 TEXT1 RESSEL 0 7 PORT_ PIN TOT0 TOT1 PPG1_T OUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN218 0x01B4 TEXT2 RESSEL 0 7 PORT_ PIN TOT0 TOT1 PPG2...

Page 81: ...14 15 RIC_RE SIN224 0x01C0 TEXT8 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFSET PPG6_T OUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN225 0x01C2 TEXT9 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFS...

Page 82: ...7 PORTSE L 8 15 OCU0_CK 1 RESSEL 0 7 FRT0 FRT1 FRT2 FRT3 FRT4 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU0_D OWNB0 RESSEL 0 7 FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB RESSEL 8 15 PO...

Page 83: ...7 PORTSE L 8 15 OCU0_MT SF0 RESSEL 0 7 FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU0_MT SF1 RESSEL 0 7 FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF...

Page 84: ...F FRT4_Z TSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU0_ZT SF1 RESSEL 0 7 FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN233 0x01D2 OCU0_M OD0...

Page 85: ...8 15 OCU1_D OWNB0 RESSEL 0 7 FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU1_D OWNB1 RESSEL 0 7 FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB...

Page 86: ...1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU1_MT SF1 RESSEL 0 7 FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU...

Page 87: ...SF0 RESSEL 0 7 FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU1_ZT SF1 RESSEL 0 7 FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF RESSEL 8 15 P...

Page 88: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN238 0x01DC OCU2_CK 0 RESSEL 0 7 FRT0 FRT1 FRT2 FRT3 FRT4 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU2_CK 1 RESSEL 0 7 FRT0 FRT1 FRT2 FRT3 FRT4 RESSEL 8 15 P...

Page 89: ...15 PORTSE L 0 7 PORTSE L 8 15 OCU2_FC MD0 RESSEL 0 7 FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU2_FC MD1 RESSEL 0 7 FRT0_F CMD FRT1_F CMD FRT2_F C...

Page 90: ...RT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU2_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTS...

Page 91: ...Resource RESSEL 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN239 0x01DE OCU2_M OD0 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE S...

Page 92: ...FRT8 FRT9 FRT10 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU8_CK 1 RESSEL 0 7 FRT8 FRT9 FRT10 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU8_D OWNB0 RESSEL 0 7 FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB RESSEL 8...

Page 93: ...MD FRT10_ FCMD RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU8_MT SF0 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10_ MTSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU8_MT SF1 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10...

Page 94: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN256 0x0200 OCU8_ZT SF0 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU8_ZT SF1 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF...

Page 95: ...e for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN258 0x0204 OCU8_M OD1 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN259 0x0206 OCU9_CK 0 RESSEL 0 7 FRT8...

Page 96: ...D OWNB FRT10_ DOWNB RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU9_D OWNB1 RESSEL 0 7 FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU9_FC MD0 RESSEL 0 7 FRT8_F CMD FRT9_F...

Page 97: ...SF FRT10_ MTSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU9_T0 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU9_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31...

Page 98: ...Resource RESSEL 3 0 PORT SEL 3 0 Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RIC_RE SIN260 0x0208 OCU9_M OD0 RESSEL 0 7 set 1 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE S...

Page 99: ...T8 FRT9 FRT10 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU10_C K1 RESSEL 0 7 FRT8 FRT9 FRT10 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU10_D OWNB0 RESSEL 0 7 FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB RESSEL 8...

Page 100: ...FRT10_ FCMD RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU10_M TSF0 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10_ MTSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU10_M TSF1 RESSEL 0 7 FRT8_M TSF FRT9_M TSF FRT10...

Page 101: ...FRT10_ ZTSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 OCU10_Z TSF1 RESSEL 0 7 FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN263 0x020E OCU10_M OD0 RESSEL 0 7 set 1 s...

Page 102: ...15 RIC_RE SIN282 0x0234 ICU0_T0 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 ICU0_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_...

Page 103: ...0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 ICU1_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSE L...

Page 104: ...0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 ICU2_T1 31 0 RESSEL 0 7 FRT0_T 31 0 FRT1_T 31 0 FRT2_T 31 0 FRT3_T 31 0 FRT4_T 31 0 RESSEL 8 15 PORTSE L 0 7 P...

Page 105: ...RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 ICU8_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN...

Page 106: ...31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 ICU9_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE...

Page 107: ..._ T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 ICU10_T1 31 0 RESSEL 0 7 FRT8_T 31 0 FRT9_T 31 0 FRT10_ T 31 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN352 0x02C0 AIN8 RESSEL 0 7 PORT_ PIN TOT...

Page 108: ...8 15 RIC_RE SIN356 0x02C8 BIN9 RESSEL 0 7 PORT_ PIN TOT17 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN357 0x02CA ZIN9 RESSEL 0 7 PORT_ PIN TOT0 PPG6_T OUT0 PPG6_T OUT2 PPG7_T OUT0 RESSEL 8 15 POR...

Page 109: ...79 0x02F6 PPG1_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT0 RLT0_U FSET FRT0_M TSF OCU0_ OTD0 RESSEL 8 15 PORTSE L 0 7 P1_16 P3_04 PORTSE L 8 15 RIC_RE SIN380 0x02F8 PPG1_TI N2 RESSEL 0 7 set 0 RE...

Page 110: ...RTSE L 0 7 PORTSE L 8 15 RIC_RE SIN384 0x0300 PPG2_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN385 0x0302 PPG3_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT1 RLT1_U FSET...

Page 111: ...CU0_ OTD0 RESSEL 8 15 PORTSE L 0 7 P1_16 P3_04 PORTSE L 8 15 RIC_RE SIN389 0x030A PPG4_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN390 0x030C PPG4_TI N3 RESSEL 0 7 set 0 RE...

Page 112: ...0x0314 PPG6_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT16 RLT16_ UFSET FRT8_M TSF OCU8_ OTD0 RESSEL 8 15 PORTSE L 0 7 P1_29 P3_20 PORTSE L 8 15 RIC_RE SIN395 0x0316 PPG6_TI N2 RESSEL 0 7 set 0 RE...

Page 113: ...TSE L 0 7 PORTSE L 8 15 RIC_RE SIN399 0x031E PPG7_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN400 0x0320 PPG8_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT16 RLT16_ UFSET...

Page 114: ...U8_ OTD0 RESSEL 8 15 PORTSE L 0 7 P1_29 P3_20 PORTSE L 8 15 RIC_RE SIN404 0x0328 PPG9_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN405 0x032A PPG9_TI N3 RESSEL 0 7 set 0 RES...

Page 115: ...8 15 RIC_RE SIN409 0x0332 PPG11_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FSET TOT17 RLT17_ UFSET FRT8_M TSF OCU8_ OTD0 RESSEL 8 15 PORTSE L 0 7 P1_29 P3_20 PORTSE L 8 15 RIC_RE SIN410 0x0334 PPG11_TI N...

Page 116: ...t 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN432 0x0360 PPG12_TI N3 RESSEL 0 7 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN433 0x0362 PPG13_TI N1 RESSEL 0 7 PORT_ PIN TOT0 RLT0_U FS...

Page 117: ..._U FSET RESSEL 8 15 PORTSE L 0 7 P2_06 P3_31 PORTSE L 8 15 RIC_RE SIN437 0x036A PPG14_TI N2 RESSEL 0 7 set 0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN438 0x036C PPG14_TI N3 RESSEL 0 7 set 0 RE...

Page 118: ...UT2 PPG3_T OUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN491 0x03D6 ADC12B0 _HWTRG 1 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU2_ OTD0 PPG0_T OUT2 PPG2_T OUT0 PPG4_T OUT0 RES...

Page 119: ...FSET OCU10_ OTD0 OCU0_ OTD0 PPG2_T OUT2 PPG4_T OUT0 PPG6_T OUT0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN496 0x03E0 ADC12B0 _HWTRG 6 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OC...

Page 120: ...ET OCU9_ OTD0 OCU0_ OTD0 PPG5_T OUT0 PPG6_T OUT2 PPG8_T OUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN501 0x03EA ADC12B0 _HWTRG 11 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OC...

Page 121: ...ET OCU8_ OTD0 OCU0_ OTD0 PPG7_T OUT2 PPG9_T OUT0 PPG11_ TOUT0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN506 0x03F4 ADC12B0 _HWTRG 16 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU...

Page 122: ...OCU2_ OTD0 OCU0_ OTD0 PPG10_ TOUT0 PPG11_ TOUT2 PPG13_ TOUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN511 0x03FE ADC12B0 _HWTRG 21 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU1_...

Page 123: ...RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU0_ OTD0 PPG12_ TOUT2 PPG14_ TOUT0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN516 0x0408 ADC12B0 _HWTRG 26 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT17_ UFSET O...

Page 124: ...TRG 30 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU1_ OTD0 PPG15_ TOUT0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN521 0x0412 ADC12B0 _HWTRG 31 RESSEL 0 7 PORT_ PIN RLT17_ UFSET...

Page 125: ...0 _HWTRG 35 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU0_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN526 0x041C ADC12B0 _HWTRG 36 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT1_U...

Page 126: ...B0 _HWTRG 40 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU0_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN531 0x0426 ADC12B0 _HWTRG 41 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT17_ U...

Page 127: ...B0 _HWTRG 45 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU0_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN536 0x0430 ADC12B0 _HWTRG 46 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT1_U F...

Page 128: ...0 _HWTRG 50 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU0_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN541 0x043A ADC12B0 _HWTRG 51 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT0_U...

Page 129: ...5 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU0_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN546 0x0444 ADC12B0 _HWTRG 56 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_...

Page 130: ...LT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU1_ OTD0 PPG1_T OUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN551 0x044E ADC12B0 _HWTRG 61 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU2_ OT...

Page 131: ...SET OCU1_ OTD0 OCU2_ OTD0 PPG0_T OUT2 PPG2_T OUT0 PPG4_T OUT0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN556 0x0458 ADC12B1 _HWTRG 2 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU...

Page 132: ...FSET OCU0_ OTD0 OCU2_ OTD0 PPG3_T OUT0 PPG4_T OUT2 PPG6_T OUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN561 0x0462 ADC12B1 _HWTRG 7 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OC...

Page 133: ...ET OCU10_ OTD0 OCU1_ OTD0 PPG5_T OUT2 PPG7_T OUT0 PPG9_T OUT0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN566 0x046C ADC12B1 _HWTRG 12 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU8...

Page 134: ...OCU9_ OTD0 OCU1_ OTD0 PPG8_T OUT0 PPG9_T OUT2 PPG11_ TOUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN571 0x0476 ADC12B1 _HWTRG 17 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU2...

Page 135: ...CU8_ OTD0 OCU1_ OTD0 PPG10_ TOUT2 PPG12_ TOUT0 PPG14_ TOUT0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN576 0x0480 ADC12B1 _HWTRG 22 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU2_...

Page 136: ...RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU1_ OTD0 PPG13_ TOUT0 PPG14_ TOUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN581 0x048A ADC12B1 _HWTRG 27 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT0_U FSET OC...

Page 137: ...B1 _HWTRG 31 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU2_ OTD0 PPG15_ TOUT2 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN586 0x0494 ADC12B1 _HWTRG 32 RESSEL 0 7 PORT_ PIN RLT0_U...

Page 138: ...B1 _HWTRG 36 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU2_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN591 0x049E ADC12B1 _HWTRG 37 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT16_ UF...

Page 139: ...1 _HWTRG 41 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU1_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN596 0x04A8 ADC12B1 _HWTRG 42 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT0_U...

Page 140: ..._HWTRG 46 RESSEL 0 7 PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU1_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN601 0x04B2 ADC12B1 _HWTRG 47 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT16_ UF...

Page 141: ...1 _HWTRG 51 RESSEL 0 7 PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU1_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN606 0x04BC ADC12B1 _HWTRG 52 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT16_ UF...

Page 142: ...1 _HWTRG 56 RESSEL 0 7 PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU1_ OTD0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN611 0x04C6 ADC12B1 _HWTRG 57 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT0_U FS...

Page 143: ...7 PORTSE L 8 15 RIC_RE SIN615 0x04CE ADC12B1 _HWTRG 61 RESSEL 0 7 PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU2_ OTD0 PPG0_T OUT0 PPG2_T OUT0 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN616...

Page 144: ...TA RT RESSEL 0 7 TOT0 TOT16 RESSEL 8 15 PORTSE L 0 7 PORTSE L 8 15 RIC_RE SIN629 0x04EA MDIO RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P0_31 P3_06 PORTSE L 8 15 RIC_RE SIN630 0x04EC CRS RESSEL 0 7 RESSEL 8...

Page 145: ...ESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P0_29 P4_07 PORTSE L 8 15 RIC_RE SIN634 0x04F4 RXD3 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P0_30 P3_05 PORTSE L 8 15 RIC_RE SIN635 0x04F6 COL RESSEL 0 7 RESSEL 8 15 POR...

Page 146: ...0 7 RESSEL 8 15 PORTSE L 0 7 P0_17 P4_00 PORTSE L 8 15 RIC_RE SIN639 0x04FE TXCLK RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P0_20 P4_03 PORTSE L 8 15 RIC_RE SIN643 0x0506 I2S0_WS RESSEL 0 7 RESSEL 8 15 POR...

Page 147: ...RG0 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P1_16 P2_10 PORTSE L 8 15 RIC_RE SIN686 0x055C ADTRG1 RESSEL 0 7 RESSEL 8 15 PORTSE L 0 7 P4_22 P1_08 P2_11 PORTSE L 8 15 Notes When both GPIO_PORTEN GPORTEN an...

Page 148: ...R0 POD 04 SCS10_0 LCDD9 ARH0_AI C1_dbg_ out_0 DSP0_G3 _0 MAD5 PPC_PCF GR005 0x000A P0_05 GPIO_PO DR0 POD 05 SCS11_0 LCDD10 ARH0_AI C1_TDA0 ARH0_AI C1_DND ATA0 DSP0_G4 _0 SOT0_1 MAD6 PPC_PCF GR006 0x00...

Page 149: ...C_1 MCSX2 PPC_PCF GR019 0x0026 P0_19 GPIO_PO DR0 POD 19 RES MCSX3 PPC_PCF GR020 0x0028 P0_20 GPIO_PO DR0 POD 20 PPC_PCF GR021 0x002A P0_21 GPIO_PO DR0 POD 21 M_SDATA 0_0 TXEN_0 M_DQ3 PPC_PCF GR022 0x0...

Page 150: ...O UT0_0 BN0 BL0 PPC_PCF GR104 0x0048 P1_04 GPIO_PO DR1 POD 04 SCK0_0 SCL0 OCU0_O TD1_0 TOT0_0 PPG0_TO UT2_0 BP0 BH0 PPC_PCF GR105 0x004A P1_05 GPIO_PO DR1 POD 05 SOT0_0 SGA0_0 SDA0 TRACE0_ 0 PPG1_TO U...

Page 151: ...0 SDA17 OCU10_ OTD1_0 TOT49_0 SYSC0_C LK_0 WOT PPC_PCF GR117 0x0062 P1_17 GPIO_PO DR1 POD 17 SCS170_ 0 PWM1P0 PPG6_TO UT0_0 PPC_PCF GR118 0x0064 P1_18 GPIO_PO DR1 POD 18 SCS171_ 0 PWM1M0 PPG6_TO UT2_0...

Page 152: ...PPC_PCF GR200 0x0080 P2_00 GPIO_PO DR2 POD 00 PWM2M3 PPG13_T OUT0_0 PPC_PCF GR201 0x0082 P2_01 GPIO_PO DR2 POD 01 SCK11_0 SCL11 PWM1P4 PPG13_T OUT2_0 PPC_PCF GR202 0x0084 P2_02 GPIO_PO DR2 POD 02 SOT...

Page 153: ...09E P2_15 GPIO_PO DR2 POD 15 SOT4_0 LCDD0 SDA4 DSP0_R2 _0 MDATA4 PPC_PCF GR216 0x00A0 P2_16 GPIO_PO DR2 POD 16 SCS40_0 LCDD1 DSP0_R3 _0 MDATA5 PPC_PCF GR217 0x00A2 P2_17 GPIO_PO DR2 POD 17 SCS41_0 LCD...

Page 154: ...R311 0x00D6 P3_11 GPIO_PO DR3 POD 11 SCS80_1 SGO1_1 PPG7_TO UT2_1 OCU1_O TD1_1 TOT1_1 TRACE1_ 1 PPC_PCF GR312 0x00D8 P3_12 GPIO_PO DR3 POD 12 SGA2_1 PPG8_TO UT0_1 OCU2_O TD0_1 TRACE2_ 1 TX1_1 PPC_PCF...

Page 155: ...CF GR325 0x00F2 P3_25 GPIO_PO DR3 POD 25 SCS20_1 I2S0_SD_ 1 PPG12_T OUT2_1 MDATA9 PPC_PCF GR326 0x00F4 P3_26 GPIO_PO DR3 POD 26 SCS21_1 I2S0_WS _1 PPG13_T OUT0_1 MDATA10 PPC_PCF GR327 0x00F6 P3_27 GPI...

Page 156: ..._PCF GR406 0x010C P4_06 GPIO_PO DR4 POD 06 PPC_PCF GR407 0x010E P4_07 GPIO_PO DR4 POD 07 PPC_PCF GR408 0x0110 P4_08 GPIO_PO DR4 POD 08 PPC_PCF GR409 0x0112 P4_09 GPIO_PO DR4 POD 09 PPC_PCF GR410 0x011...

Page 157: ...PC_PCF GR424 0x0130 P4_24 GPIO_PO DR4 POD 24 PPC_PCF GR425 0x0132 P4_25 GPIO_PO DR4 POD 25 PPC_PCF GR426 0x0134 P4_26 GPIO_PO DR4 POD 26 PPC_PCF GR427 0x0136 P4_27 GPIO_PO DR4 POD 27 PPC_PCF GR428 0x0...

Page 158: ...ating conditions Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not re...

Page 159: ...grid array BGA packages with Sn Ag Cu balls are mounted using Sn Pb eutectic soldering junction strength may be reduced under some conditions of use Storage of Semiconductor Devices Because plastic c...

Page 160: ...abnormal operation In such cases use anti static measures or processing to prevent discharges 3 Corrosive Gases Dust or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical...

Page 161: ...ate and then open them or set them to the input state and handle them in the same way as input pins About Power Supply Pins If the device has multiple VCC and VSS pins the device is designed in such a...

Page 162: ...to Switch Off VCC12 during Power Off Sequence During power off sequence it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode power domain 2 off If VCC12 needs to be switch...

Page 163: ...VCC5 0 3 V Output voltage 1 VO1 VSS 0 3 VCC5 0 3 V 5 V pins not shared SMC VO2 VSS 0 3 DVCC 0 3 V 5 V pins shared SMC VO3 VSS 0 3 VCC3 0 3 V 3 V pins VO4 VSS 0 3 VCC53 0 3 V 5 V 3 V pins Maximum clam...

Page 164: ...mW 40 125 o C PD 1100 mW System Thermal Resistance Theta j a1 17 o C W TEQFP 208 The minimum value depends on the system specification of heat radiation The described value is estimated under the con...

Page 165: ...r drive current is low such as in the low power consumption modes the B input potential can increase the potential at the VCC pin via a protective diode possibly affecting other devices Note that if t...

Page 166: ...pin does not exceed rated values at any time regardless of instantaneously or constantly when the B signal is input Do not leave B input pins open Example of a recommended circuit WARNING Semiconduct...

Page 167: ...ion The B signal should always be applied by connecting a limiting resistor between the B signal and the microcontroller The value of the limiting resistor should be set so that the current input to t...

Page 168: ...AVCC3_DAC 2 7 3 6 V Smoothing capacitor CS C 4 7 F Tolerance of up to 40 Operating temperature TA 40 105 o C PD 2000 mW TA 40 125 o C PD 1100 mW 1 For S6J33xxxSx or S6J33xxxUx or S6J33xxxTx or S6J33xx...

Page 169: ...ESCAUSEUR Register cannot be guaranteed so these flags should don t care by software processing For the connections of smoothing capacitor CS see the following diagram C Pin Connection Diagram CS C VS...

Page 170: ...standard 3 One layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90 or more The layer can be used for system ground 4 35 or more of the die...

Page 171: ...4 P1_03 to P1_16 P3_08 to P3_23 P4_08 to P4_23 CMOS hysteresis input level is selected 0 7 VCC5 VCC5 0 3 V VIH5 Automotive input level is selected 0 8 VCC5 VCC5 0 3 V VIH6 P1_09 P1_10 P1_15 P1_16 TTL...

Page 172: ...P1_16 P3_08 to P3_23 P4_08 to P4_23 CMOS hysteresis input level is selected Vss 0 3 0 3 VCC5 V VIL5 Automotive input level is selected Vss 0 3 0 5 VCC5 V VIL6 P1_09 P1_10 P1_15 P1_16 TTL input level...

Page 173: ...to P4_23 CMOS hysteresis input level is selected 0 05 V CC5 V VHYS5 Automotive input level is selected 0 03 V CC5 V VHYS6 P1_09 P1_10 P1_15 P1_16 TTL input level is selected 0 035 V VHYS7 P1_17 to P1...

Page 174: ...0 V IOH 2 0 mA VOH4 P1_03 to P1_16 P3_08 to P3_23 P4_08 to P4_23 VCC5 4 5 V IOH 1 0 mA VCC5 0 5 VCC5 V VOH5 VCC5 4 5 V IOH 2 0 mA VCC5 0 5 VCC5 V VOH6 VCC5 4 5 V IOH 5 0 mA VCC5 0 5 VCC5 V VOH7 PSC_1...

Page 175: ...onditions Value Unit Remarks Min Typ Max H level output voltage VOH19 P2_12 VCC53 4 5 V IOH 1 0 mA VCC53 0 5 VCC53 V ODR 1 0 2b00 VOH20 VCC53 3 0 V IOH 0 5 mA VOH21 VCC53 4 5 V IOH 2 0 mA VCC53 0 5 VC...

Page 176: ...VCC53 3 0 V IOL 2 0 mA VOL4 P1_03 to P1_16 P3_08 to P3_23 P4_08 to P4_23 VCC5 4 5 V IOL 1 0 mA 0 0 4 V VOL5 VCC5 4 5 V IOL 2 0 mA 0 0 4 V VOL6 VCC5 4 5 V IOL 5 0 mA 0 0 4 V VOL7 PSC_1 VCC5 4 5 V IOL 2...

Page 177: ...er Symbol Pin Name Conditions Value Unit Remarks Min Typ Max L level output voltage VOL19 P2_12 VCC53 4 5 V IOL 1 0 mA 0 0 4 V ODR 1 0 2b00 VOL20 VCC53 3 0 V IOL 0 5 mA VOL21 VCC53 4 5 V IOL 2 0 mA 0...

Page 178: ...P2 P0_00 to P0_20 P1_03 to P1_31 P2_00 to P2_19 P3_00 to P3_31 P4_00 to P4_31 Pull up resistor selected 25 50 100 k 5 V pins 5 V 3 V pins RUP3 P0_21 to P0_31 P1_00 to P1_02 Pull up resistor selected 1...

Page 179: ...Value Unit Remarks Min Typ Max Power supply current ICC12 VCC12 Normal operation 315 775 mA TA 40 105 C CPU 240MHz HPM 120 MHz CPU 200 MHz HPM 200 MHz GDC 200 MHz 395 mA Example use case 1 TA 40 105...

Page 180: ...N PD4_1 ON 440 860 A TA 25 C 8 MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 430 830 A TA 25 C 8 MHz crystal for main oscillator PD1 ON 110 430 A TA 25 C 32 kHz crystal for sub oscillato...

Page 181: ...N 335 620 A TA 25 C 4 MHz crystal for main oscillator PD1 ON 420 705 A TA 25 C 8 MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 415 700 A TA 25 C 8 MHz crystal for main oscillator PD1 ON PD4...

Page 182: ...0 0 mA Maximum deviation of VOH13 90 mV High current output drive capacity Phase to phase deviation2 Delta VOL13 DVCC 4 5 V IOL 30 0 mA Maximum deviation of VOL13 90 mV LCD divider resistor RLCD V0 to...

Page 183: ...locked tPJ 10 10 ns Internal Slow CR oscillation frequency FCRS 50 100 150 kHz Internal Fast CR oscillation frequency FCRF 2 40 4 00 5 61 MHz Before trim 3 20 4 00 4 81 MHz After trim Notes The maxim...

Page 184: ...ing TA Recommended operating conditions Vcc5 5 0 V 10 VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Source oscillation clock frequency FCL X0A X1A 32 768 kHz...

Page 185: ...clock 4 FCLK_CPU0 240 200 180 MHz FCLK_SHE 240 200 180 MHz FCLK_FCLK 80 66 7 90 MHz FCLK_ATB 120 100 90 MHz FCLK_DBG 120 100 90 MHz FCLK_HPM 120 200 180 MHz FCLK_HPM2 60 100 90 MHz FCLK_DMA 120 200 18...

Page 186: ...66 7 60 MHz FCLK_SYSC0P 80 66 7 60 MHz FCLK_COMP 80 66 7 60 MHz 1 Target maximum clock frequencies when CPU clock 240MHz 2 Target maximum clock frequencies when CPU clock 200MHz 3 Target maximum clock...

Page 187: ...ge Note CPU will be reset when the power supply voltage is equal to or less than LVD setting voltage 5 5 4 5 3 5 2 4 Maximum frequency of each clock Frequency MHz Power supply V CC 5 V 1 21 1 09 2 4 M...

Page 188: ...8 60 120 160 240 8 4 8 16 120 240 16 8 16 32 240 Oscillation circuit example Note For the configuration of an oscillation circuit request the oscillator manufacturer to perform a circuit matching eva...

Page 189: ...0 20 30 40 Series 9 1 4 4 Reset Input TA Recommended operating conditions Vcc5 5 0 V 10 VSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Reset input time tRSTL RSTX 10 s Width...

Page 190: ...ld below 1 5 V for a minimum period of tOFF 3 Power ramp rate must be 1 V us or less from 1 5 V to 2 6 V Power on can detect by satisfying power ramp rate when power off time is satisfied 4 This speci...

Page 191: ...S DVSS 0 0 V VCC12 1 15 V 0 06 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH SCK0 to SCK4 SCK8 to SCK12 tCLK_LCPnA 1 10 ns SCK16 to SCK17 tCLK_COMP...

Page 192: ...e CL 20 pF IOL 5 mA IOH 5 mA 8tCLK_LCPnA 1 ns SCK16 to SCK17 8tCLK_COMP ns SCK SOT delay time tSLOVI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SOT0 SOT1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT1...

Page 193: ...lid SIN SCK setup time tIVSHE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 to SIN17 10 ns SCK Valid SIN hold time tSHIXE 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SC...

Page 194: ...Document Number 002 10635 Rev I Page 194 of 325 S6J3310 20 30 40 Series Slave mode tSLSH VIL tSLOVE tIVSHE tSHIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL tF VIH VIL VIH tSHSL tR VIH...

Page 195: ...Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 Master Mode CL 20 pF IOL 5 mA IOH 5 mA 8tCLK_LCPnA 1 ns SCK16 to SCK17 8tCLK_COMP ns SCK...

Page 196: ...K8 to SCK12 4tCLK_LCPnA 1 ns SCK16 to SCK17 4tCLK_COMP ns SCK SOT delay time tSHOVE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SOT0 to SOT4 SOT8 to SOT12 SOT16 to SOT17 40 ns Valid SIN SCK setup time t...

Page 197: ...I Page 197 of 325 S6J3310 20 30 40 Series Master mode tSCYC VOH tSHOVI tIVSLI tSLIXI VIH VIL VOH VOL SCK SOT SIN VIH VIL VOL Slave mode tSHSL VIL tSHOVE tIVSLE tSLIXE VIH VIL VOH VOL SCK SOT SIN VIH V...

Page 198: ...SOT1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT12 SOT16 to SOT17 30 30 ns Valid SIN SCK setup time tIVSLI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 SIN1 SIN2_1 SIN3_1 SIN4 SIN8 to SIN12 SIN1...

Page 199: ...K setup time tIVSLE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 to SIN17 10 ns SCK Valid SIN hold time tSLIXE 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16...

Page 200: ...002 10635 Rev I Page 200 of 325 S6J3310 20 30 40 Series Slave mode tSLSH VIL tF tSLIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL VIH VOH VOL tIVSLE tSHOVE VIL VIH VIH VIL tSHSL tR Changes when writing to t...

Page 201: ...0 SOT1 SOT2_1 SOT3_1 SOT4 SOT8 to SOT12 SOT16 to SOT17 30 30 ns Valid SIN SCK setup time tIVSHI SCK0 SCK1 SCK2_1 SCK3_1 SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 SIN1 SIN2_1 SIN3_1 SIN4 SIN8 to SIN12 SIN...

Page 202: ...K setup time tIVSHE SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 to SIN17 10 ns SCK Valid SIN hold time tSHIXE 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16...

Page 203: ...002 10635 Rev I Page 203 of 325 S6J3310 20 30 40 Series Slave mode tSHSL VIL tR tSHIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL VIH VOH VOL tIVSHE tSLOV E VIL VIH VIH VIL tSLSH tF Changes when writing to t...

Page 204: ...S0x SCS1x SCS2x_1 SCS3x_1 SCS4 SCS8x to SCS12x tCSDS 3 15 5tCLK_LCPnA 4 ns SCS16x to SCS17x tCSDS 3 15 5tCLK_COMP ns SCS SCK setup time tCSSI SCK2_0 SCK3_0 SCS2x_0 SCS3x_0 Master Mode CL 20 pF IOL 10...

Page 205: ...LCPnA 4 10 ns 1 tCSSU SCSTR CSSU 7 0 x serial chip select timing operating clock 2 tCSHD SCSTR CSHD 7 0 x serial chip select timing operating clock 3 tCSDS SCSTR CSDS 15 0 x serial chip select timing...

Page 206: ...de SCK input SOT Normal synchronous transfer SOT SPI compatible tCSSE SCS input tCSHE tCSDE tDSE tDEE VIL VIL VIH VIH VIL VIH VOL VOL VOH Clock switching example by master mode round operation x y 0 1...

Page 207: ...SCS0x SCS1x SCS2x_1 SCS3x_1 SCS4 SCS8x to SCS12x tCSDS 3 15 5tCLK_LCPnA 4 ns SCS16x to SCS17x tCSDS 3 15 5tCLK_COMP ns SCS SCK setup time tCSSI SCK2_0 SCK3_0 SCS2x_0 SCS3x_0 Master Mode CL 20 pF IOL 1...

Page 208: ...LCPnA 4 10 ns 1 tCSSU SCSTR CSSU 7 0 x serial chip select timing operating clock 2 tCSHD SCSTR CSHD 7 0 x serial chip select timing operating clock 3 tCSDS SCSTR CSDS 15 0 x serial chip select timing...

Page 209: ...de SCK input SOT Normal synchronous transfer SOT SPI compatible tCSSE SCS input tCSHE tCSDE tDSE tDEE VIL VIL VIH VIH VIH VIL VOL VOL VOH Clock switching example by master mode round operation x y 0 1...

Page 210: ...CS0x SCS1x SCS2x_1 SCS3x_1 SCS4 SCS8x to SCS12x tCSDS 3 15 5 tCLK_LCPnA 4 ns SCS16x to SCS17x tCSDS 3 15 5tCLK_COMP ns SCS SCK setup time tCSSI SCK2_0 SCK3_0 SCS2x_0 SCS3x_0 Master Mode CL 20 pF IOL 1...

Page 211: ...K_LCPnA 4 10 ns 1 tCSSU SCSTR CSSU 7 0 x serial chip select timing operating clock 2 tCSHD SCSTR CSHD 7 0 x serial chip select timing operating clock 3 tCSDS SCSTR CSDS 15 0 x serial chip select timin...

Page 212: ...mode SCK input SOT Normal synchronous transfer SOT SPI compatible tCSSE SCS input tCSHE tCSDE tDSE tDEE VIH VIH VIL VIH VIL Clock switching example by master mode round operation x y 0 1 2 3 x and y a...

Page 213: ...CS0x SCS1x SCS2x_1 SCS3x_1 SCS4 SCS8x to SCS12x tCSDS 3 15 5tCLK_LCPnA 4 ns SCS16x to SCS17x tCSDS 3 15 5tCLK_COMP ns SCS SCK setup time tCSSI SCK2_0 SCK3_0 SCS2x_0 SCS3x_0 Master Mode CL 20 pF IOL 10...

Page 214: ...nd operation CL 20 pF IOL 10 mA IOH 10 mA 4tCLK_LCPnA 4 0 4tCLK_LCPnA 4 10 ns 1 tCSSU SCSTR CSSU 7 0 x serial chip select timing operating clock 2 tCSHD SCSTR CSHD 7 0 x serial chip select timing oper...

Page 215: ...patible tCSSI SCS output tCSHI tCSDI VOH VOH VOL VOL VOH VIH Slave mode SCK input SOT Normal synchronous transfer SOT SPI compatible tCSSE SCS input tCSHE tCSDE tDSE tDEE VIH VIL VIL VOL VOL VOH Clock...

Page 216: ...S 0 0 V VCC12 1 15 V 0 06 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH SCK0 to SCK4 SCK8 to SCK12 tCLK_LCPnA 1 10 ns SCK16 to SCK17 tCLK_COMP 10 n...

Page 217: ...old time SCL SDA tHDDAT 0 3 45 2 0 0 9 3 s Data setup time SDA SCL tSUDAT 250 100 ns Stop condition setup time SCL SDA tSUSTO 4 0 0 6 s Bus free time between stop condition and start condition tBUF 4...

Page 218: ...Document Number 002 10635 Rev I Page 218 of 325 S6J3310 20 30 40 Series SDA SCL tHDSTA tLOW tHDDAT tSUDAT tHIGH tSUSTA tHDSTA tSP tBUF tSUSTO...

Page 219: ...N0 ICU0_IN1 to ICU2_IN1 ICU8_IN1 to ICU10_IN1 4tCLK_LCPnA 2 ns 4tCLK_LCPnA 2 100 ns 100 4tCLK_LCPnA 2 100 ns FRT0_TEXT to FRT4_TEXT FRT8_TEXT to FRT10_TEXT 4tCLK_LCPnA 3 ns 4tCLK_LCPnA 3 100 ns 100 4t...

Page 220: ...IN pin L level to BIN fall tADBD AIN8 to AIN9 BIN8 to BIN9 PC_Mode2 or PC_Mode3 Time from BIN pin L level to AIN rise tBDAU AIN8 to AIN9 BIN8 to BIN9 PC_Mode2 or PC_Mode3 Time from BIN pin H level to...

Page 221: ...Document Number 002 10635 Rev I Page 221 of 325 S6J3310 20 30 40 Series AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN...

Page 222: ...Document Number 002 10635 Rev I Page 222 of 325 S6J3310 20 30 40 Series ZIN AIN BIN ZIN...

Page 223: ...c 5 0 V 10 Vcc53 5 0 V 10 3 3 V 0 3 V VSS DVSS 0 0 V VCC12 1 15 V 0 06 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTRGH tTRGL EINT0 to EINT23 100 ns ADTRG0 to...

Page 224: ...S6J3310 20 30 40 Series 9 1 4 10 NMI Input TA Recommended operating conditions Vcc5 5 0 V 10 VSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tNMIL NMIX 300...

Page 225: ...er supply voltage has exceeded the detection voltage range 2 Please suppress the change of the power supply within the range of the power supply voltage regulation to do a low voltage detection by det...

Page 226: ...supply voltage rises Low voltage detection time TRd 30 s 1 If the power fluctuation time is less than the low voltage detection time TRd and has passed the detection voltage range the detection may oc...

Page 227: ...LVDL0 channel is potentially below supply range defined in 9 1 2 Recommended Operating Condition Low voltage detection internal low voltage detection for LVDL1 TA Recommended operating conditions VSS...

Page 228: ...mended operating conditions VCC5 VCC53 DVCC 5 0 V 10 VCC3 3 3 V 0 3 V VCC12 1 15 V 0 06 V VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Output rise fall time...

Page 229: ...itions Value Unit Remarks Min Max Clock Cycle tDC0CYC DSP0_CLK CL 20 pF IOL 15 mA IOH 15 mA 25 ns Output delay from DSP0_CLK tDC0D DSP0_R7 0 DSP0_G7 0 DSP0_B7 0 DSP0_EN DSP0_HSYNC DSP0_VSYNC CL 20 pF...

Page 230: ...herwise dH is calculated as the following dH The number rounding division ratio x 0 5 down to the nearest integer division ratio division ratio is multiplication value among SYSDIV bit HPMDIV bit and...

Page 231: ...me without MRDY tCYC MCLK 2 mA is selected in ODR bit in PPC_PCFGR register 62 5 ns Cycle time with MRDY tCYC MCLK 62 5 ns If using MRDY set MCLK to 20 MHz or less CS delay time tCSO MCLK MCSX0 to MCS...

Page 232: ...Symbol Pin Name Conditions Value Unit Remarks Min Max Data setup time tDSR MOEX MDATA00 to MDATA15 CMOS Schmitt input and Disable noise filter are selected in PPC_PCFGR register 21 tcy c ns Data hold...

Page 233: ...ameter Symbol Pin Name Conditions Value Unit Remarks Min Max MWEX delay time tWEO MCLK MWEX 2 mA is selected in ODR bit in PPC_PCFGR register 0 5 18 ns Byte mask delay time tWRO MCLK MDQM0 to MDQM1 0...

Page 234: ...cnt 0 31 5 ns M_SDATA M_SLCK Input setup time tisdata M_SDATA0_0 3 M_SDATA1_0 3 1 ns M_SLCK M_SDATA Input hold time tihdata M_SDATA0_0 3 M_SDATA1_0 3 1 ns M_SCLK M_SDATA Output delay time toddata M_SD...

Page 235: ...M_SDATA1_0 3 1 ns M_SCLK M_SDATA Output delay time toddata M_SDATA0_0 3 M_SDATA1_0 3 tcyc 4 1 5 ns M_SCLK M_SDATA Output hold time tohdata M_SDATA0_0 3 M_SDATA1_0 3 Tcyc 4 1 0 ns M_SCLK M_SSEL Output...

Page 236: ...DLP function VOH VOL VOH VOL VOH VOL VOH VOL tcyc VIH VIL G_SCLK0 G_SDATA0_0 3 G_SDATA1_0 3 input timing VOH VOH VIH VIL valid tisdata delayed sample clock tihdata VOH tspcnt G_SDATA0_0 3 G_SDATA1_0...

Page 237: ...cycle tCKCYC M_CK CL 20 pF IOL 10 mA IOH 10 mA 10 0 ns CS CK Chip Select setup time tCSS M_CS _1 2 tCKCYC 2 0 ns DQ CK Input setup time tIS M_DQ7 0 1 25 ns CK DQ Input hold time tIH M_DQ7 0 1 25 ns CK...

Page 238: ...CKCYC 2 0 ns DQ CK Input setup time tIS M_DQ7 0 1 25 ns CK DQ Input hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 tCKCYC 2 ns RWDS CK Data Mask Valid tDMV M_RWDS 1 ns CK RWD...

Page 239: ...etup time tCSS M_CS _1 2 tRDSCYC 2 0 ns DQ CK Setup time tIS M_DQ7 0 1 25 ns CK DQ Hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 tRDSCYC 2 ns RDS DQ Setup time tDSS M_DQ7 0...

Page 240: ...0 1 25 ns CK DQ Hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 tRDSCYC 2 ns RWDS DQ valid Setup time tDSS M_DQ7 0 0 8 ns RWDS DQ invalid Hold time tDSH M_DQ7 0 0 8 ns CK RWDS...

Page 241: ...ting conditions Vcc53 Vcc3 3 3 V 0 3 V VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max RXCLK cycle tRXCYC RXCLK 40 0 ns RX setup time tRXS RXER RXDV RXD0 3 10 0 ns...

Page 242: ...Symbol Pin Name Conditions Value Unit Remarks Min Max TXCLK cycle tTXCYC TXCLK CL 20 pF IOL 5 mA IOH 5 mA 40 0 ns COL CRS input setup time tCRXS COL CRS 12 0 ns COL CRS input hold time tCRXH COL CRS...

Page 243: ...eter Symbol Pin Name Conditions Value Unit Remarks Min Max MDC cycle tMDCYC MDC CL 20 pF IOL 5 mA IOH 5 mA 400 0 ns MDIO input setup time tMDIS MDIO 100 0 ns MDIO input hold time tMDIH MDIO 0 0 ns MDI...

Page 244: ...0 internal frequency MLBCLK external frequency 2 MediaLB Output Timing TA Recommended operating conditions Vcc3 3 3 V 0 3 V VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks...

Page 245: ...Noise Filter TA Recommended operating conditions VCC5 VCC53 DVCC5 5 0 V 10 VSS DVSS AVSS 0 0 V Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Width for input removal ALL GPIO 17 ns In...

Page 246: ...ignal uncertainty tUNCERT CS 5 0 ns Output to input duration tOUT2IN LCDD0 17 25 0 ns For setup active and hold calculation the following has to be considered signal to signal uncertainty has to be ad...

Page 247: ...power on tRV12 VCC12 14 2 ms Note VDLAT VRDLAT VRDLBT and VRHYS are referred to 9 1 4 11 Low Voltage Detection External Voltage VOH7 is referred to 9 1 3 DC Characteristics LVDH1 reset need to be alw...

Page 248: ...tFV12RST and tRV12RST are referred to 9 1 4 22 Power and Reset Sequence 1 Battery Disconnect All supplies fall together 2 VCC12 can be fully depleted or not full depleted 3 DVCC VCC53 and VCC3 can st...

Page 249: ...30 40 Series Note VCC12 controlled by PSC_1 VCC12 can be fully deplete Case2 1 PSC_1 H L H transition by User Program VCC12 RSTX VCC5 PSC_1 No timing specification of VCC12 and RSTX VCC5 VDLAT VRDLAT...

Page 250: ...S6J3310 20 30 40 Series Note VCC12 and AVCC5 controlled by PSC_1 VCC53 VCC3 AVCC3_DAC and DVCC controlled by PSC_1 Can be controlled by VCC5 GPIO also 1 VCC12 can be fully depleted or not full deplete...

Page 251: ...5 us Note If the sequence given in VCC5 and VCC12 sequence cannot be applied this sequence can be applied VDLAT VRDLAT VRDLAT and VRHYS are referred to 9 1 4 11 Low Voltage Detection External Voltage...

Page 252: ...TX Sequence cannot be applied this sequence can be applied Connect RSTX signal and MODE signal outside of the MCU and shorten the trace length between MCU and these two signal lines The following assu...

Page 253: ...put current IAIN AN0 to AN30 AN32 to AN38 1 0 1 0 A AVSS VAIN AVCC5 AN31 AN39 to AN63 2 0 2 0 A Analog input voltage VAIN AN0 to AN63 AVRL AVRH V Reference voltage AVRH AVRH5 4 5 6 5 5 6 V AVcc5 AVRH...

Page 254: ...When the external impedance is too high the analog voltage sampling time may become insufficient In this case we recommend attaching a capacitor about 0 1 F to an analog input pin Analog input circuit...

Page 255: ...or Deviation from the ideal value of the input voltage required for changing the output code by 1 LSB Total error Difference between the actual value and the theoretical value The total error Total er...

Page 256: ...utput changes from 0x000 to 0x001 VFST Voltage for which digital output changes from 0xFFE to 0xFFF FFF FFE FFD 004 003 002 001 AVRL AVRH AVRH Actual conversion characteristics 1 LSB N 1 VZT N 1 AVRL...

Page 257: ...fc 20 kHz 82 72 dB SNR 3 signal frequency 1 kHz LPF fc 20 kHz A weighting filter 85 89 dB Dynamic range 3 83 86 dB Out of Band Energy 20 kHz to 64 fs 33 dB Channel Separation 80 dB Output impedance 15...

Page 258: ...Startup Time Time sec EN V AOUTS V Startup Time 10mV Last Voltage VDD 0V 0V Start up time can be calculated as follows 1 Start up time TYP 650 ms 4 2 CCOM 10 F 1 100 CCOM is a capacitor connected to T...

Page 259: ...C2 0 1 F ceramic capacitors C3 C4 2 2 F low ESR capacitors Impedance of each power line must be as low as possible Notes When DAC is not used in your system the related pins should be AVCC3_DAC GND a...

Page 260: ...m level overhead time excluded 2 Erase count Data retention time Program 1 000 20 years Temperature at write erase time Average temperature TA 85 degrees Celsius Erase count Data retention time Work 1...

Page 261: ...IPCU Inter processor communication unit IRC Interrupt controller IRQ Interrupt request ISR Interrupt service routine JTAG Joint test action group Acronym Description LLPP Low latency peripheral port L...

Page 262: ...34EJBESE20000 176 pin plastic TEQFP LEV176 S6J334EJTESE20000 176 pin plastic TEQFP LEV176 S6J334EJEESE20000 176 pin plastic TEQFP LEV176 S6J334DJTESE20000 176 pin plastic TEQFP LEV176 S6J334DJEESE2000...

Page 263: ...gured by the application The message itself is syntactically correct and can be received by other nodes The occurrence of the limitation requires a certain relationship in time between a transmission...

Page 264: ...an be applied in order to detect messages which contain wrong ID and control filed information A checksum covering arbitration and control fields can be added to the data field of the message to be tr...

Page 265: ...002 10635 Rev I Page 265 of 325 S6J3310 20 30 40 Series 13 Appendix 13 1 Application 1 JTAG Tool Connection This is an application example of JTAG tool connection See the relevant application note 002...

Page 266: ...33 38 AN48 Correct TEQFP144 Analog input port 12bit ADC AN4 7 AN10 11 AN14 15 AN25 26 AN28 30 10 3 Product Description 3 2Product description Revised 4MHz to 16MHz as below Error A wide range of 3 6 4...

Page 267: ...rrent conditions at the design stage Correct 1 Preventing Over Voltage and Over Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause dete...

Page 268: ...2Recomme nded operating condition Revised Rating Min Spec as below Error Power supply voltage VCC5 Rating Min 2 6 Power supply voltage VCC3 Rating Min 2 6 Correct Power supply voltage VCC5 Rating Min...

Page 269: ...CLK_HAPP1B0 Value Max 1 60MHz Correct Internal clock frequency FCLK_HAPP1B0 Value Max 1 80MHz 180 9 Electric Characteristics 9 1 4 5 Power on Conditions Revised as below Error Parameter Symbol Pin Nam...

Page 270: ...0 30 40 2 and 3 must be satisfied When neither 2 nor 3 can be satisfied assert external reset RSTX at power up and any brownout event Power off time Power ramp rate VCC tOFF 0 2V 0 2V dV dt 2 6V Corre...

Page 271: ...ection External Voltage Revised as below Low voltage detection 1 15 V power supply low voltage detection Error Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Detection voltage aft...

Page 272: ...tion voltage range Correct Parameter Sym bol Pin Name Conditi ons Value Uni t Remarks Min Typ Max Supply voltage range VRDP5 1 05 1 21 V Detection voltage VRDL 1 0 75 0 85 0 95 V When power supply vol...

Page 273: ...n power supply voltage falls 3 Detection voltage after trimming VRDLAT 1 0 844 0 875 0 906 V When power supply voltage falls Typ 3 5 2 3 Hysteresis width VRHYS 75 mV When power supply voltage rises Lo...

Page 274: ...A Output hold time tohdata M_SDATA0_0 3 M_SDATA1_0 3 3 5 ns M_SCLK M_SSEL Output delay time todsel M_SSEL0 1 5 5 ns tcyc 4 5ns M_SCLK M_SSEL Output hold time tohsel M_SSEL0 1 4 5 ns Notes This is Targ...

Page 275: ...put delay time todsel M_SSEL0 1 7 0 ns tcyc 3 0ns M_SCLK M_SSEL Output hold time tohsel M_SSEL0 1 3 0 ns Notes This is Target Spec Correct 2 DDR HSSPI Interface Timing DDR mode Parameter Symbol Pin Na...

Page 276: ...tCSS M_CS _1 2 CL 20pF IOL 10mA IOH 10mA tCKCYC 2 0 ns CK CS Chip select hold time tCSH M_CS _1 2 tCKCYC 2 ns 228 9 Electric Characteristics 9 1 4 17 Hyper BUS Revised as below Error 16 2 Hyper Bus W...

Page 277: ...hold time tIH M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH M_CS _1 2 0 ns RDS DQ valid RDS transition to DQ valid tDSS M_DQ7 0 0 8 0 8 ns RDS DQ invalid RDS transition to DQ invalid tDSH M_DQ7 0...

Page 278: ...DQ valid tDSS M_DQ7 0 0 8 0 8 ns RWDS DQ invalid RWDS transition to DQ invalid tDSH M_DQ7 0 0 8 0 8 ns CK RWDS Refresh Indicator Valid tRIV M_RWDS 6 ns CK RWDS Hi z Refresh Indicator Hold tRIH M_RWDS...

Page 279: ...pec Correct 1 MediaLB Input Timing Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MLBCLK cycle tmckc MLBCLK 40 0 ns MLBSIG MLBDAT Input hold tdhmcf MLBSIG MLBDAT 4 0 ns Notes This is...

Page 280: ...describes another A D converter function do not refer it A D Channel Control Register ADC12Bn_CHCTRL0 bit5 0 ANIN 5 0 Analog Input Selection bits This register setting is possible of channel 0 31 the...

Page 281: ...2 to inactivate the operation of VCC12 supplied domain below the operation assurance range 164 9 Electric Characteristics 9 1 2 Recommended operating condition Revised as below Error The detection rel...

Page 282: ...SSCG_PLL is used with down spread the MAX value of the frequency is standardized This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated Correct Note that Ta 125 condit...

Page 283: ...I2 C bus device can be used on a standard mode I2 C bus system as long as the device satisfies the requirement of tSUDAT 250 ns 216 9 Electric Characteristics 9 1 4 11 Low Voltage Detection External V...

Page 284: ...although the detection level is below the minimum operation guarantee voltage the LVD reset factor flag is set as the voltage drops below the detection level 218 9 Electric Characteristics 9 1 4 12 L...

Page 285: ...Min Max Address hold time tAH D C CL 20pF IOL 5mA IOH 5mA 20 ns Address setup time tAW D C 20 ns Write cycle time tCYCW CS WR 100 ns Write Enable pulse H width tCCHW CS WR 35 ns Write Enable pulse L w...

Page 286: ...time tAW D C R W 20 ns Write cycle time tCYCW CS E 100 ns Write Enable pulse H width tEH CS E 35 ns Write Enable pulse H widthtEH CS E 35 ns Write Enable pulse L width tEL CS E 35 ns Write data set ti...

Page 287: ...oftware engineer 002 07884 Application note The reference software sample application the reference board design and so on are explained Software and hardware engineer Under consideration Correct Docu...

Page 288: ...340 Remark Sound waveform generator 1 unit x 5 outputs No See 2 2 1 I2S 2 ch 1ch One only supports an output as a function of the sound system 5 6 2 Function List 2 1 Product lineup Error Function S6J...

Page 289: ...3 and 5 and PD6 Correct Power Domain PD The product series supports the power off control of PD1 PD2 including PD3 and 5 PD4_0 PD4_1 and PD6 17 18 19 20 4 Package and Pin Assignment 4 1 1 TEQFP 208 Pi...

Page 290: ...44 S6J331xHyz Figure 4 10 TEQFP 144 S6J332xHyz add Figure 4 11 TEQFP 144 S6J333xHyz add Figure 4 12 TEQFP 144 S6J334xHyz add 29 4 Package and Pin Assignment 4 2 1 TEQFP208 Error Correct Revised PKG fi...

Page 291: ...125 o C PD 1100mW 172 9 Electric Characteristics 9 1 2 Recommended operating condition Error Operating temperature TA 40 105 o C PD 2000mW TA 40 125 o C PD 1200mW Correct Operating temperature TA 40...

Page 292: ...ed except for the low voltage detector Note that although the detection level is below the minimum operation guarantee voltage the LVD reset factor flag is set as the voltage drops below the detection...

Page 293: ...mode 370 810 A TA 25 C 4MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 360 780 A TA 25 C 4MHz crystal for main oscillator PD1 ON PD4_0 ON or PD4_1 ON 350 750 A TA 25 C 4MHz crystal for main...

Page 294: ...off time tOFF VCC5 100 s 2 226 253 9 Electric Characteristics 9 1 4 11Low Voltage Detection External Voltage 9 1 5 A D converter Error S6J33xxxSC S6J33xxxUC S6J33xxxTC S6J33xxxVC S6J33xxxAC S6J33xxxBC...

Page 295: ...detection voltage and the minimum operation assurance voltage MCU functions are not guaranteed except for the low voltage detector Note that although the detection level is below the minimum operatio...

Page 296: ...tween this detection voltage and the minimum operation assurance voltage MCU functions are not guaranteed except for the low voltage detector Note that although the detection level is below the minimu...

Page 297: ...ow voltage detection time TRd 30 s 4 2 This detection voltage level setting is below the minimum operation assurance voltage Between this detection voltage and the minimum operation assurance voltage...

Page 298: ...is width VRHYS 75 mV When power supply voltage rises Low voltage detection time TRd 30 s 3 2 This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU opera...

Page 299: ...08 pin plastic TEQFP TEQFP208 S6J331EKBC 208 pin plastic TEQFP TEQFP208 S6J331EKAC 208 pin plastic TEQFP TEQFP208 S6J331EJCC 176 pin plastic TEQFP TEQFP176 S6J332EJCC 176 pin plastic TEQFP TEQFP176 S6...

Page 300: ...FP LEW176 S6J334CJEx 176 pin plastic TEQFP LEW176 S6J334CJTx 176 pin plastic TEQFP LEW176 S6J334DJEx 176 pin plastic TEQFP LEW176 S6J334DJTx 176 pin plastic TEQFP LEW176 S6J334EJAx 176 pin plastic TEQ...

Page 301: ...wer supply voltage 1 2 VCC12 VSS 0 3 VSS 1 8 V VCC12 AVCC5 169 9 Electric Characteristics 9 1 1 Absolute Maximum Rating Error Total maximum clamp current ICLAMP 50 mA SPECIAL SPEC A Correct Total maxi...

Page 302: ...C3_DAC VCC12 Note that power supplies inside can be turned on in arbitrary order Corresponding Part number is S6J33xxxSC or S6J33xxxUC or S6J33xxxTC or S6J33xxxVC or S6J33xxxBC or S6J33xxxDC or S6J33x...

Page 303: ...ore and the thickness should be 1 6 mm or more JEDEC standard 3 One layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90 or more The layer ca...

Page 304: ...nditions Value Unit Remarks Min Typ Max Power supply current ICC12 VCC 12 Normal operation 320 800 mA TA 40 105 C CPU 240MHz HPM 120MHz CPU 200MHz HPM 200MHz GDC 200MHz 395 mA Example use case 1 TA 40...

Page 305: ...el overhead time excluded 1 256bit write time Program 40 512 s System level overhead time excluded 1 Page mode write time Program 320 4096 s System level overhead time excluded 1 32bit write time Work...

Page 306: ...1 Basic option Error Figure 2 1 Correct Figure 2 1 Option and Part Number for S6J3310 20 30 40 Series 7 2 Function List 2 2 1 Basic option Error Revision Revision version Correct Revision 8 2 Functio...

Page 307: ...002 10635 Rev I Page 307 of 325 S6J3310 20 30 40 Series Page Section Change Results 17 18 19 20 21 22 23 24 25 26 27 28 4 Package and Pin Assignment 4 1 Pin Assignment Error z C D Revision Correct z...

Page 308: ...e 350 850 mA TA 40 105 C CPU 240MHz HPM 120MHz CPU 200MHz HPM 200MHz GDC 200MHz ICCH12 Timer Stop Mode 430 mA ICC5 VCC5 Normal operation 45 85 mA Flash write erase 100 mA Correct Parameter Symbol Pin...

Page 309: ...A TA 25 C 4 MHz crystal for main oscillator PD1 ON 420 705 A TA 25 C 8 MHz crystal for main oscillator PD1 ON PD4_0 ON PD4_1 ON 415 700 A TA 25 C 8 MHz crystal for main oscillator PD1 ON PD4_0 ON or...

Page 310: ...C D Revision Correct x C D E Revision Rev G 6 2 Function List 2 1 Function List Function CRC Error 1 unit Correct 4 units 6 2 Function List 2 1 Function List Function DDR HSSPI Error 2 ch Correct 1 ch...

Page 311: ...taneously inputting L level to RSTX pin and inputting L level to MD pin Release factor Inputting H level to RSTX pin See the TraveoTM Platform hardware manual in detail Following resets are not mounte...

Page 312: ...s series Correct Only 2 ports of MFS have the dedicated I O for I2 C See I2 C timing in 9 1 4 6 Multi Function Serial in detail The I2 C is not designed to be hot swappable CTS RTS is not mounted hard...

Page 313: ...0 000 5 years Temperature at write erase time Average temperature TA 85 degrees Celsius 1 Guaranteed value for up to 1 000 erases 2 Guaranteed value for up to 100 000 erases 3 Target Value Correct Par...

Page 314: ...engineer 002 07884 Correct Document Type Definition Primary User Document Code S6J3310 20 30 40 Datasheet This document The function and its characteristics are specified quantitatively Investigator...

Page 315: ..._03 to P1_16 P3_08 to P3_23 P4_08 to P4_23 CMOS hysteresis input level is selected 0 05 VCC5 V VHYS5 Automotive input level is selected 0 03 VCC5 V VHYS6 P1_09 P1_10 P1_15 P1_16 TTL input level is sel...

Page 316: ...clock 4 PLL2 output clock 4 PLL3 output clock 4 188 9 Electric Characteristics 9 1 4 3 Internal Clock Timing Added the below 4 sentence Error none Correct 4 The PLLx SSCGx cannot set under 200MHz 195...

Page 317: ...n plastic TEQFP LEV176 S6J332CJBx 176 pin plastic TEQFP LEV176 S6J332CJTx 176 pin plastic TEQFP LEV176 S6J332EJBx 176 pin plastic TEQFP LEV176 S6J334BJDx 176 pin plastic TEQFP LEV176 S6J334CJEx 176 pi...

Page 318: ...TEQFP LEV176 S6J334EJBESE20000 176 pin plastic TEQFP LEV176 S6J334EJTESE20000 176 pin plastic TEQFP LEV176 S6J334EJEESE20000 176 pin plastic TEQFP LEV176 S6J334DJTESE20000 176 pin plastic TEQFP LEV176...

Page 319: ...40 Series Page Section Change Results 11 3 Product Description 3 2 Product Description Table 3 1 Product Features Added the below Correct Feature Description A D Converter AN39 to AN63 are not suppor...

Page 320: ...lock external address match VLAN tag Wakeup On Lan IEEE 1588 and IEEE 802 1AS Support MAC PFC Priority Based Pause Frame Support Energy Efficient Ethernet support LPI Operation in Cadence IP 802 1Qav...

Page 321: ...4 TEQFP 176 TEQFP 208 PPG0_TOUT0_1 Base timer 1 output pin 1 8 8 11 Correct Port Name Description Package Pin Number Remark TEQFP 144 TEQFP 176 TEQFP 208 PPG0_TOUT0_1 Base timer 0 output pin 1 8 8 11...

Page 322: ...Port Name Description Package Pin Number Remark TEQFP 144 TEQFP 176 TEQFP 208 PPG10_TOUT0_1 Base timer 20 output pin 1 98 114 47 6 Port Description 6 1 Port Description List Table 6 1 S6J3310 Series...

Page 323: ...Pitch correct from the provisional version to the formal version TYPO I2 C Fast Mode For detail see Major Changes C 5622186 MATO 02 07 2017 ID add ICCT ICCH spec add LCD bus I F spec revise Power and...

Page 324: ...f Change Submission Date Description of Change For detail see Major Changes I 6300353 GSHI 09 05 2018 Add an option limitation for Description of A D Converter of Product Description Update Ethernet S...

Page 325: ...ftware is prohibited TO THE EXTENT PERMITTED BY APPLICABLE LAW CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE INCLUDING...

Page 326: ...JTESE20000 S6J334CKSESE20000 S6J334BJDESE20000 S6J332CJTDSE20000 S6J332CKSDSE20000 S6J332EJBDSE20000 S6J334CJBESE20000 S6J334CJEESE20000 S6J334DHEESE20000 S6J334DHFESE20000 S6J334EHEESE20000 S6J334EJB...

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