Document Number: 002-10635 Rev. *I
Page
240 of 325
S6J3310/20/30/40 Series
(4) Hyper Bus Read Timing (HyperRAM)
(T
A
: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, V
SS
= DV
SS
= AV
SS
= 0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit Remarks
Min
Max
Hyper Bus clock
cycle
t
RDSCYC
M_CK
(CL = 20 pF,
I
OL
= -10 mA,
I
OH
= 10 mA),
10.0
-
ns
CS↑↓ -> CK↑
Chip Select setup
time
t
CSS
M_CS#_1,2
t
RDSCYC
-2.0
-
ns
DQ -> CK↑↓
Setup time
t
IS
M_DQ7-0
1.25
-
ns
CK↑↓ -> DQ
Hold time
t
IH
M_DQ7-0
1.25
-
ns
CK↓ -> CS↑
Chip select hold time
t
CSH
M_CS#_1,2
t
RDSCYC
/2
-
ns
RWDS↑↓> DQ (valid)
Setup time
t
DSS
M_DQ7-0
-0.8
-
ns
RWDS↑↓> DQ
(invalid)
Hold time
t
DSH
M_DQ7-0
-0.8
-
ns
CK↑ -> RWDS↑↓
Refresh Indicator
Valid
t
RIV
M_RWDS
-
6
ns
CK↑ -> RWDS (Hi-z)
Refresh Indicator
Hold
t
RIH
M_RWDS
0
-
ns
Notes: This is Target Spec.
V
IH
V
OH
t
CSS
V
OL
V
IL
CA0
47-40
CA0
39-
32
CA1
31-24
CA1
23-16
CA2
15-8
CA2
7-0
Dn
15-8
Dn
7-0
V
OL
t
RIH
t
RIV
t
CSHI
t
CSM
t
PO
t
RWR
t
IS
t
DSH
t
DQLZ
V
OH
V
OH
t
CSS
t
CSH
Dn+1
15-8
Dn+1
7-0
t
IH
t
DSS
t
OZ
t
DSZ
t
CKDS
t
RDSCYC
G_CK
M_CK
G_RWDS
M_RWDS
G_DQ7~0
M_DQ7~0
G_CS#_1,2
M_CS#_1,2
V
OH
V
OL
