Document Number: 002-10635 Rev. *I
Page
246 of 325
S6J3310/20/30/40 Series
9.1.4.21
LCD Bus I/F
(T
A
: Recommended operating conditions, Vcc53 = 5.0 V ± 10 % / 3.3 V ± 0.3 V, V
SS
= 0.0 V, VCC12 = 1.15 V ± 0.06 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Clock cycle time
tCLK
WR#, RD#
(CL = 20 pF,
I
OL
= -5 mA,
I
OH
= 5 mA),
12.5
-
ns
−
Signal-to-Signal
uncertainty
tUNCERT
CS#
-
5.0
ns
−
Output to input
duration
tOUT2IN
LCDD0-17
-
25.0
ns
−
For setup, active and hold calculation
the following has to be considered:
-> signal-to-signal uncertainty has to
be added to tAW, tAH, tDS, tDH
-> max_input_delay and
max_output_delay has to be added
to tACC
CS#
WR#, RD#
LCDD (write)
LCDD (read)
tUNCERT
t
tACC
n
x tCLK
Note:
−
In order to calculate interface timing, refer to the LCD controller specification of the external display for the required AC
characteristics and S6J3300 Series Hardware Manual.
