Document Number: 002-10635 Rev. *I
Page
247 of 325
S6J3310/20/30/40 Series
9.1.4.22
Power and Reset Sequence
VCC5 and VCC12 sequence
(T
A
: Recommended operating conditions, V
SS
= 0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Wait time from LVDH1
level detection to
falling VCC12
t
FV12
VCC12
-
0.6
-
ms
−
VCC12 stabilization
time during power-on
t
RV12
VCC12
-
-
14.2
ms
−
Note:
−
VDLAT, VRDLAT, VRDLBT and VRHYS are referred to "
Low Voltage Detection (External Voltage)
".
VOH7 is referred to "
".
−
LVDH1 reset need to be “always enable”. For details, see the Traveo™ Platform Hardware Manual.
−
The above sequence needs not to be applied in the following cases the application enters PSS mode:
“VCC12 is controlled by PSC_1 at entry and exit from PSS mode” (Normal Sequence).
VCC12
RSTX
VCC5
PSC_1
No timing specification of VCC12 and RSTX
V
RDLBT
+V
RHYS
V
RDLAT
V
DLAT
t
FV12
t
RV12
V
OH7
