Cypress S6J331EJSESE20000, Manual

Page: 248 / 326

Document Number: 002-10635 Rev. *I Page
248 of 325
S6J3310/20/30/40 Series
Note:
−
RSTX controlled by VCC5.
−
VCC12 and AVCC5 controlled by PSC_1.
−
VCC53, VCC3, AVCC3_DAC and DVCC controlled by PSC_1. Can be controlled by VCC5 GPIO also.
−
VDLAT, VDLBT and VHYS are referred to " 9.1.4.11 Low Voltage Detection (External Voltage) ".
VRDLAT, VRDLBT and VRHYS are referred to “ 9.1.4.12 Low Voltage Detection (Internal Voltage) ".
VOH7, VIL9 and VIH9 are referred to " 9.1.3 DC Characteristics ".
t
RV12
, t
FV12RST
and t
RV12RST
are referred to “ 9.1.4.22 Power and Reset Sequence ”.
*1: Battery Disconnect: All supplies fall together.
*2: VCC12 can be fully depleted or not full depleted.
*3: DVCC, VCC53 and VCC3 can start before or after VCC12.
*4:VCC5 is higher than level detection voltage: VDLAT+VHYS
VCC5 is lower than level detection voltage: VDLBT+VHYS
VDLAT, VDLBT and VHYS are referred to "
9.1.4.11 Low Voltage Detection (External Voltage) ".
*5:VCC5 is higher than level detection voltage: VRHYS
VCC5 is lower than level detection voltage: VRHYS
VRDLAT, VRDLBT and VRHYS are referred to "
9.1.4.11 Low Voltage Detection (External Voltage) ".
Case1) "PSC_1 H --> L --> H transition by VCC5”