Document Number: 002-10635 Rev. *I
Page
192 of 325
S6J3310/20/30/40 Series
CSIO timing (SMR:MD2-0 = 0b010)
(1) Normal Synchronous Transfer (SCR:SPI = 0) and Mark Level "H" of Serial Clock Output (SMR:SCINV = 0)
(T
A
: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ± 10 % /3.3 V ± 0.3 V,
Vcc53 = 5.0 V ±10 % / 3.3 V ± 0.3 V, V
SS
= DV
SS
= 0.0 V, V
CC
12 = 1.15 V ± 0.06 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Serial clock
cycle time
t
SCYC
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12
Master
Mode
(CL = 20 pF,
I
OL
= -5 mA,
I
OH
= 5 mA)
8t
CLK_LCPnA
*1
-
ns
-
SCK16 to SCK17
8t
CLK_COMP
-
ns
SCK ↓ → SOT
delay time
t
SLOVI
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0, SOT1,
SOT2_1,
SOT3_1, SOT4,
SOT8 to SOT12,
SOT16 to SOT17
-30
+30
ns
Valid SIN → SCK
↑
setup time
t
IVSHI
SCK0, SCK1,
SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0, SIN1, SIN2_1,
SIN3_1, SIN4,
SIN8 to SIN12,
SIN16 to SIN17
40
-
ns
SCK ↑→ Valid SIN
hold time
t
SHIXI
0
-
ns
Serial clock
cycle time
t
SCYC
SCK2_0, SCK3_0
Master
Mode
(CL = 20 pF,
I
OL
= -10 mA,
I
OH
= 10 mA)
2t
CLK_LCPnA
*1
-
ns
-
SCK ↓ → SOT
delay time
t
SLOVI
SCK2_0, SCK3_0,
SOT2_0, SOT3_0
-7.5
+7.5
ns
Valid SIN → SCK
↑
setup time
t
IVSHI
SCK2_0, SCK3_0,
SIN2_0, SIN3_0
10
-
ns
SCK ↑→ Valid SIN
hold time
t
SHIXI
0
-
ns
