Document Number: 002-00833 Rev. *L
Page 16 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
6.5.1
JEDEC Device ID
The Joint Electron Device Engineering Council (JEDEC) standard JEP106T defines a method for reading the manufacturer ID and
device ID of a compliant memory. This information is primarily intended for programming equipment to automatically match a device
with the corresponding programming algorithm.
The JEDEC ID information is structured to work with any memory data bus width e.g. x8, x16, x32. The code values are always byte
wide but are located at bus width address boundaries such that incrementing the device address inputs will read successive byte,
word, or double word locations with the codes always located in the least significant byte location of the data bus. Because the data
bus is word wide each code byte is located in the lower half of each word location and the high order byte is always zero.
6.5.2
Common Flash Memory Interface
The Common Flash Interface (CFI) specification defines a standardized data structure that may be read from a flash memory
device, which allows vendor-specified software algorithms to be used for entire families of devices. The data structure contains
information for system configuration such as various electrical and timing parameters, and special functions supported by the
device. Software support can then be device-independent, JEDEC ID-independent, and forward-and-backward-compatible for the
specified flash device families.
The system can read CFI information at the addresses within the selected sector as shown in
Section 11.2, Device ID and Common
Flash Memory Interface Address Map on page 59
.
Like the JEDEC Device ID information, CFI information is structured to work with any memory data bus width e.g. x8, x16, x32. The
code values are always byte wide but are located at data bus width address boundaries such that incrementing the device address
reads successive byte, word, or double word locations with the codes always located in the least significant byte location of the data
bus. Because the data bus is word wide each code byte is located in the lower half of each word location and the high order byte is
always zero.
For further information, please refer to the Cypress CFI Version 1.4 (or later) Specification and the Cypress CFI Publication 100 (see
also JEDEC publications JEP137-A and JESD68.01). Please contact JEDEC
for their standards and the
Cypress CFI Publications may be found at the Cypress Web site
(
http://www.cypress.com/appnotes/CFI_v1.4_VendorSpec_Ext_A1.pdf
at the time of this document’s publication).
6.5.3
Secured Silicon Region
The Secured Silicon region provides an extra Flash memory area that can be programmed once and permanently protected from
further changes. The Secured Silicon Region is 512 bytes in length. It consists of 256 bytes for factory data and 256 bytes for
customer-secured data.
The Secured Silicon Region (SSR) is overlaid in the sector address specified by the SSR enter command.
6.5.4
Configuration Register
The Configuration Register Enter command is only valid when written to a bank that is in Read mode. The configuration register
mode address map appears within, and replaces Flash Array data of, the selected sector address range. The meaning of the
configuration register bits is defined in the configuration register operation description. In configuration register mode, a write of
00F0h to any address will return the sector to Read mode.
Table 9. Secured Silicon Region
Byte Address Range
Secure Silicon Region
Size
(SA) + 0000h to 00FFh
Factory
256 Bytes
(SA) + 0100h to 01FFh
Customer
256 Bytes
