Document Number: 002-00833 Rev. *L
Page 69 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
Figure 29. Synchronous Read Wrapped Burst - AADM Interface
Figure 30. Synchronous Read Followed By Read Burst - AADM Interface
AH
AL
t
CEZ
t
RACC
t
CEZ
t
RACC
t
RACC
t
CR
t
OEZ
t
BDH
t
BACC
t
OE
t
ACH
t
ACS
t
AVDH
t
AVDS
t
AVDH
t
AVDP
t
AVDS
t
CES
t
IA
15 initial access cycles setting shown.
t
IA
measured from CLK rising edge during AVD# Low
to CLK rising edge at beginning of first data out.
OE# enables data output only after the Address-Low cycle in which AVD# is Low and OE# is High.
OE# is ignored after OE# returns high between accesses until the next Address-Low is received.
OE# low with AVD# low signals the presence of Address-High.
The Address-High cycle is optional. When the high part of address does
not change only the Address-Low cycle is needed.
CLK
CE#
AVD#
OE#
WE#
A/DQ15-A/DQ0
RDY(with data)
RDY(before data)
AH
AL
AH
AL
t
RACC
t
RACC
t
RACC
t
CEZ
t
RACC
t
RACC
t
RACC
t
RACC
t
CR
t
OEZ
t
BACC
t
OE
ASIC_t
CO
t
OEZ
t
BDH
t
BACC
t
OE
t
ACH
t
ACS
t
AVDH
t
AVDS
t
AVDH
t
AVDP
t
AVDS
t
CES
t
IA
t
IA
CLK
CE#
AVD#
OE#
WE#
A/DQ15 - A/DQ0
RDY(with data)
RDY(before data)
