Document Number: 002-00833 Rev. *L
Page 26 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
Notes:
1. Bit 7 is set when there is no erase or program operation in progress in the device.
2. Bits 1 through 6 are valid if and only if Bit 7 is set.
Notes:
1. Upon issuing the “Erase Suspend” Command, the user must continue to read status until DRB becomes 1 before accessing another sector within the same bank.
2. Cleared by “Erase Resume” Command.
Notes:
1. ESB bit reflects “success” or “failure” of the most recent erase operation.
2. Cleared by “Clear Status Register” Command as well as by hardware reset.
Table 22. Status Register - Bit 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device Ready
Bit.
Overall status
Erase Suspend
Status Bit
Erase Status Bit Program Status
Bit
RFU
Program
Suspend Status
Bit
Sector Lock
Status Bit
Bank Status Bit
DRB
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
0
Device busy
programming or
erasing
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
VALID
1
Device ready
VALID
VALID
VALID
VALID
VALID
VALID
VALID
Table 23. Status Register - Bit 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device Ready
Bit.
Overall status
Erase Suspend
Status Bit
Erase Status Bit Program Status
Bit
RFU
Program
Suspend Status
Bit
Sector Lock
Status Bit
Bank Status Bit
DRB
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
1
Bits 6:1 only
valid when Bit 7
= 1
0
No Erase in
Suspension
X
X
X
X
X
X
1
Bit 6:1 only valid
when Bit 7 = 1
1
Erase in
Suspension
X
X
X
X
X
X
Table 24. Status Register - Bit 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device Ready
Bit.
Overall status
Erase Suspend
Status Bit
Erase Status Bit Program Status
Bit
RFU
Program
Suspend Status
Bit
Sector Lock
Status Bit
Bank Status Bit
DRB
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
1
Bits 6:1 only
valid when Bit 7
= 1
X
0
Erase successful
X
X
X
X
X
1
Bit 6:1 only valid
when Bit 7 = 1
X
1
Erase error
X
X
X
X
X
