Document Number: 002-00833 Rev. *L
Page 65 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
Figure 21. Asynchronous Read - AADM Interface
Figure 22. Asynchronous Read Followed By Read - AADM Interface
Add-Hi
Add-Low
Data
t
CR
t
CR
t
CEZ
t
OEZ
t
ACC
t
ACC
t
CE
t
OE
t
AVDP
t
AVDP
t
AVDP
t
AAVDH
t
AAVDH
t
AAVDS
t
AAVDS
t
AAVDH
t
AAVDH
t
AAVDS
t
AAVDS
t
CAS
OE# enables data output only after the Address-Low cycle in which AVD# is Low and OE# is High
OE# is ignored after OE# returns high between accesses until the next Address-Low is received
OE# low with AVD# low signals the presence of Address-High.
The Address-High cycle is optional. When the high part of address does
not change only the Address-Low cycle is needed.
CE#
AVD#
OE#
WE#
A/DQ15-
A/DQ0
RDY
CLK
CLK may be at V
IL
or V
IH
or Active
AH
AL
D
AH
AL
D
t
CEZ
t
CR
t
OEZ
t
CEZ
t
ACC
t
ACC
t
OEZ
t
ACC
t
ACC
t
CE
t
OE
t
AAVDH
t
AAVDS
tAAVDH
t
AAVDS
t
WEA
t
OEH
t
AVDO
t
AVDO
t
AAVDH
t
AAVDS
t
AVDP
t
t
CAS
CLK may be at V
IL
or V
IH
or Active
CLK
CE#
AVD#
OE#
WE#
A/DQ15-
A/DQ0
RDY
t
OE
