Document Number: 002-00833 Rev. *L
Page 50 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
10.9.2
AC Characteristics–Asynchronous Read
Notes:
1. Not 100% tested.
2. If OE# is disabled before CE# is disabled, the output goes to High-Z by t
OEZ
.
If CE# is disabled before OE# is disabled, the output goes to High-Z by t
CEZ
.
If CE# and OE# are disabled at the same time, the output goes to High-Z by t
OEZ
.
Figure 14. Asynchronous Mode Read - ADM Interface
Notes:
1. AVD# Transition occurs after CE# is driven to Low and Valid Address Transition occurs before AVD# is driven to Low.
2. VA = Valid Read Address, RD = Read Data.
Parameter
Symbol
Min
Max
Unit
Access Time from CE# Low
t
CE
–
80
ns
Asynchronous Access Time from address valid
t
ACC
–
80
Read Cycle Time
t
RC
80
–
AVD# Low Time
t
AVDP
6
–
Address Setup to rising edge of AVD#
t
AAVDS
4
–
Address Hold from rising edge of AVD#
t
AAVDH
3.5
–
Output Enable to Output Valid
t
OE
–
15
CE# Setup to AVD# falling edge
t
CAS
0
–
CE# Disable to Output & RDY High-Z
t
CEZ
–
10
OE# Disable to Output High-Z
t
OEZ
–
10
AVD# High to OE# Low
t
AVDO
4
–
CE# low to RDY valid
t
CR
–
10
WE# Disable to AVD# Enable
t
WEA
9.6
–
WE# Disable to OE# Enable
t
OEH
4
–
t
CE
WE#
Amax
–
A16
CE#
OE#
Valid RD
t
ACC
t
OEH
t
OE
A/DQ15
–
A/DQ0
t
OEZ
t
AAVDH
t
AVDP
t
AAVDS
AVD#
RA
RA
Hi-Z
Hi-Z
RDY
t
CR
t
CEZ
t
CAS
