Document Number: 002-00833 Rev. *L
Page 27 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
Notes:
1. PSB bit reflects “success” or “failure” of the most recent program operation.
2. Cleared by “Clear Status Register” Command as well as by hardware reset.
Notes:
1. This Register is reserved for future use.
2. Cleared by “Clear Status Register” Command as well as by hardware reset.
Notes:
1. Upon issuing the “Program Suspend” Command, the user must continue to read status until DRB becomes 1 before accessing another sector within the same bank.
2. Cleared by “Program Resume” Command.
Table 25. Status Register - Bit 4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device Ready Bit.
Overall status
Erase Suspend
Status Bit
Erase Status Bit Program Status
Bit
RFU
Program
Suspend Status
Bit
Sector Lock
Status Bit
Bank Status Bit
DRB
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
1
Bits 6:1 only valid
when Bit 7 = 1
X
X
0
Program
successful
X
X
X
X
1
Bit 6:1 only valid
when Bit 7 = 1
X
X
1
Program fail
X
X
X
X
Table 26. Status Register - Bit 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device Ready
Bit.
Overall status
Erase Suspend
Status Bit
Erase Status Bit Program Status
Bit
RFU
Program
Suspend Status
Bit
Sector Lock
Status Bit
Bank Status Bit
DRB
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
1
Bits 6:1 only valid
when Bit 7 = 1
X
X
X
X
X
X
X
Table 27. Status Register - Bit 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device Ready
Bit.
Overall status
Erase Suspend
Status Bit
Erase Status Bit Program Status
Bit
RFU
Program
Suspend Status
Bit
Sector Lock
Status Bit
Bank Status Bit
DRB
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
1
Bits 6:1 only
valid when Bit 7
= 1
X
X
X
X
0
No Program in
suspension
X
X
1
Bit 6:1 only valid
when Bit 7 = 1
X
X
X
X
1
Program in
suspension
X
X
