Cypress S29VS128R Manual Download

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Document Number: 002-00833 Rev. *L

Page 72 of 74

S29VS256R
S29VS128R
S29XS256R
S29XS128R

12. Revision History

Document History Page

Document Title: S29VS256R/S29VS128R/S29XS256R/S29XS128R, 256/128-Mbit (32/16 Mbyte), 1.8 V, 16-bit Data Bus,
Multiplexed MirrorBit

Flash

Document Number: 002-00833

Rev.

ECN No.

Orig. of

Change

Submission

Date

Description of Change

–

WIOB

05/15/2008 Initial release

–

WIOB

08/01/2008

DC Characteristics

Changed some values in the CMOS Compatible table

Device ID and Common Flash Memory Interface Address Map

Changed some values in the ID/CFI Data table

Memory Address Map

Added memory address map

–

WIOB

09/12/2008

Physical Dimensions/Connection Diagrams

Updated ball positions

–

WIOB

03/10/2009

Blank Check Command

Functional in Asynchronous Read Mode only

DC Characteristics

Changed some ICCB values

Global

Added 108 MHz; removed 66 MHz

–

WIOB

05/26/2010

Global

Modified document title

Features

Clarified some points

Ordering Information and Valid Combinations

Added Industrial Temperature range option

Address/Data Interface

Corrected typo

Device Bus Operations

Table

Corrected A/DQ15-A/DQ0 column information for Asynchronous Read

Asynchronous Read

Clarified asynchronous read operation.

S29XS-R AADM Access

Clarified asynchronous AADM read access.

S29VS-R ADM Access

Standardized logic Low and High descriptions to VIL and VIH. Clarified wait

states required by initial access and internal boundary crossings.

S29XS-R AADM Access

Standardized logic Low and High descriptions to VIL and VIH. Clarified wait

states required by initial access and internal boundary crossings.

Writing Commands/Command Sequences

Clarified device behavior.

Program/Erase Operations

Removed redundant information.

Sector Lock Range Command

Clarified Sector Lock Range behavior

Figure Synchronous Read Mode

Added “ADM Interface” label

Figure Asynchronous Mode Read

Added “ADM Interface” label

Figure Asynchronous Program Operation Timings

Added “ADM Interface” label

Figure Back-to-Back Read/Write Cycle Timings

Added “ADM Interface” label

Summary of Contents for S29VS128R

Page 1: ...tion Suspend and Resume commands for Program and Erase operations Asynchronous program operation independent of burst control register settings VPP input pin to reduce factory programming time Support...

Page 2: ...30 Program Erase Operations 30 Handshaking 37 Hardware Reset 37 Software Reset 37 Sector Protection Unprotection 39 Sector Lock Unlock Command 39 Sector Lock Range Command 39 Hardware Data Protection...

Page 3: ...with Publication Number S29VS_XS R_SP S29VS 256 R xx BH W 00 0 Packing Type 0 Tray standard see note Note 1 3 13 inch Tape and Reel Model Number 00 Top 01 Bottom Temperature Range W Wireless 25 C to 8...

Page 4: ...rnally RDY Output Ready Indicates when valid burst data is ready to be read CLK Input The first rising edge of CLK in conjunction with AVD low latches address input and activates burst mode operation...

Page 5: ...Bank Address RESET VPP WE CE AVD RDY DQ15 DQ0 STATE CONTROL COMMAND REGISTER Bank 1 X Decoder Y Decoder Latches and Control Logic Bank 0 X Decoder Y Decoder Latches and Control Logic DQ15 DQ0 DQ15 DQ...

Page 6: ...in FBGA packages Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods The package and or data integrity may be compromised if the package body is exposed to...

Page 7: ...002 00833 Rev L Page 7 of 74 S29VS256R S29VS128R S29XS256R S29XS128R 4 2 2 VDJ044 44 Ball Very Thin Fine Pitch Ball Grid Array 6 2 mm x 7 7 mm Figure 3 VDJ044 44 Ball Very Thin Fine Pitch Ball Grid A...

Page 8: ...ange of data which can be erased to an all Ones state Most of the sectors are 128 KBytes each Depending on the option ordered either the top 4 sectors or the bottom 4 sectors are 32 KBytes each These...

Page 9: ...a bank is returned to Read mode from EA mode In EA mode the Flash memory array data in a bank is stable but undefined and effectively unavailable for read access from the host system While in EA mode...

Page 10: ...transfer of 16 bits to the memory device and the device will store all 16 bits to a register In the case of a program operation all 16 bits of each word to be programmed will be stored in the Flash ar...

Page 11: ...ess pattern x000000h x1FFFFh Table 2 System Versus Flash View of Address System Address Signals a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 System Byte Address Hex A A A Binary Pattern 1 0 1 0 1 0 1 0 1 0 1...

Page 12: ...Bottom Boot Bank Size Mbit Sector Count Sector Size Kbyte Bank Sector Range Address Range word Address Range byte Notes 32 4 32 0 SA000 000000h 003FFFh 000000h 007FFFh Sector Starting Address Sector...

Page 13: ...Interface S29XS256R and S29XS128R Signal input and output I O connections on a high complexity component such as an Application Specific Integrated Circuit ASIC are a limited resource Reducing signal...

Page 14: ...e in burst mode this implies at least one cycle of CE or OE High before an Address high for a new access may be placed on the bus so that there is time for the memory to recognize the end of the previ...

Page 15: ...cess enter the Autoselect ID or CFI overlay will cause the now combined ID CFI address map to appear A write at any sector address in bank zero having the least significant byte address value of AAh w...

Page 16: ...structured to work with any memory data bus width e g x8 x16 x32 The code values are always byte wide but are located at data bus width address boundaries such that incrementing the device address re...

Page 17: ...y the CU in the execution of commands Typical command operations are programming or erasing of data in the Flash array All other banks are available for read access while the one bank is in EA mode Th...

Page 18: ...in at VIH during the one cycle that AVD is at VIL The data appears on A DQ15 A DQ0 when CE remains at VIL after OE is driven to VIL and the synchronous access times are satisfied The next data in the...

Page 19: ...nitial Wait States 0 10 13 wait states D0 D1 D2 D3 D4 D5 D6 D7 2 ws 1 D8 1 D1 D2 D3 D4 D5 D6 D7 1 ws 2 ws D8 2 D2 D3 D4 D5 D6 D7 1 ws 1 ws 2 ws D8 3 D3 D4 D5 D6 D7 1 ws 1 ws 1 ws 2 ws D8 4 D4 D5 D6 D7...

Page 20: ...d Initial Wait Subsequent Clock Cycles After Initial Wait States 0 7 wait states D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 1 ws D8 D9 3 D3 D4 D5 D6 D7 1 ws 1 ws D8 D9...

Page 21: ...rd Initial Wait Subsequent Clock Cycles After Initial Wait States 0 4 wait states D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 D8 D9 D10 3 D3 D4 D5 D6 D7 D8 D9 D10 D11 4...

Page 22: ...19 As an example if the starting address in the 8 word mode is system byte address 3Ch the address range to be read would be byte address 30 3Fh and the burst sequence would be 3C 3E 30 32 34 36 38 3...

Page 23: ...efore attempting burst operations The Configuration Register can also be read using a command sequence see Table 43 on page 57 The table below describes the register settings and indicates the default...

Page 24: ...Initial data is valid on the 4th rising CLK edge after addresses are latched 0011 Initial data is valid on the 5th rising CLK edge after addresses are latched 1011 13th Default 1100 Reserved 1101 Rese...

Page 25: ...le before data is valid When this bit is zero the RDY signal indicates data is valid in the same cycle the data is valid When this bit is one the RDY signal indicates data is valid one cycle before da...

Page 26: ...tus Bit DRB ESSB ESB PSB RFU PSSB SLSB BSB 0 Device busy programming or erasing Invalid Invalid Invalid Invalid Invalid Invalid VALID 1 Device ready VALID VALID VALID VALID VALID VALID VALID Table 23...

Page 27: ...Bit Sector Lock Status Bit Bank Status Bit DRB ESSB ESB PSB RFU PSSB SLSB BSB 1 Bits 6 1 only valid when Bit 7 1 X X 0 Program successful X X X X 1 Bit 6 1 only valid when Bit 7 1 X X 1 Program fail...

Page 28: ...ogram Status Bit RFU Program Suspend Status Bit Sector Lock Status Bit Bank Status Bit DRB ESSB ESB PSB RFU PSSB SLSB BSB 1 Bits 6 1 only valid when Bit 7 1 X X X X X 0 Sector not locked during operat...

Page 29: ...blank or not Bit 5 of the Status Register will be cleared to zero if the sector is erased and set to one if not erased Bit 7 Bit 0 of the Status Register will show if the device is performing a Blank...

Page 30: ...identify the write as a command to the device The upper portion of the address may also select the bank or sector in which the command operation is to be performed A Bank Address BA is the set of add...

Page 31: ...ystem attempts to load data outside this range the operation aborts after the Write to Buffer command is executed and the device will indicate a Program Fail in the Status Register at bit location 4 P...

Page 32: ...ge begins at addresses evenly divisible by 0x20 UINT16 src source_of_data address of source data UINT16 dst destination_of_data flash destination address UINT16 wc words_to_program 1 word count minus...

Page 33: ...er just as in the standard program operation See Status Register on page 25 for more information The system must write the Program Resume command to exit the Program Suspend mode and continue the prog...

Page 34: ...an determine the status of the erase operation by reading the Status Register See Status Register on page 25 for information on these status bits Once the sector erase operation has begun only reading...

Page 35: ...n not read data from the device The system can determine the status of the erase operation by reading the Status Register See Status Register on page 25 for information on these status bits Once the c...

Page 36: ...of the program operation by reading the Status Register just as in the standard program operation To resume the sector erase operation the system must write the Erase Resume command The device will re...

Page 37: ...high impedance When CE input and OE input is Low the A DQ15 A DQ0 output signals are actively driven When both of the CE inputs are High or the OE input is High the A DQ15 A DQ0 outputs are high imped...

Page 38: ...ple of using the reset function Refer to the Cypress Low Level Driver User s Guide available on www cypress com for general information on Cypress Flash memory software development guidelines Example...

Page 39: ...ycles are first written addresses are x555h and x2AAh and data is 60h During the third cycle the sector address SLA and load sector address command 61h is written This cycle sets the lower sector addr...

Page 40: ...cure Silicon Region Protection Bit is bit 1 All other bits in this register return 1 If the Customer Secure Silicon Region Protection Bit is set to 0 the Customer Secure Silicon Region is protected an...

Page 41: ...til power is removed from the device See Command Definition Table Secure Silicon Region Command Table Appendix Table 43 on page 57 for address and data requirements for both command sequences The Secu...

Page 42: ...pecification 9 2 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode and while the device is not in a suspended state The device automati...

Page 43: ...Duration of the short circuit should not be greater than one second 4 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only...

Page 44: ...IN VSS to VCC VCC VCCmax 1 A ILO Output Leakage Current VOUT VSS to VCC VCC VCCmax 1 A ICCB VCC Active burst Read Current CE VIL OE VIH WE VIH burst length 8 83 MHz 35 38 mA 104 MHz 108 MHz 39 44 mA C...

Page 45: ...TA 25 C f 1 0 MHz 2 Sampled not 100 tested ICC6 VCC Sleep Current 4 CE VIL OE VIH 20 40 A IPP Accelerated Program Current 5 CE VIL OE VIH VPP 9 5 V VPP 7 10 mA VCC 25 28 mA VIL Input Low Voltage VIO...

Page 46: ...capacitance CL 30 pF Transition time tT input rise and fall times 83 MHz 2 50 ns 104 MHz 1 85 ns 108 MHz 1 85 ns Transition time tT CLK input rise and fall times 83 MHz 2 50 ns 104 MHz 1 85 ns 108 MH...

Page 47: ...p from improper initialization a hardware reset can be used to initialize the part correctly Normal precautions must be ensured for supply decoupling to stabilize the VCC and VIO power supplies Each d...

Page 48: ...hronous burst read See AC Characteristics Table Figure 12 CLK Characterization Parameter Description 108 MHz Unit fCLK CLK Frequency Max 108 MHz Min DC 1 tCLK CLK Period Min 9 26 ns tCL tCH CLK Low Hi...

Page 49: ...6 9 26 ns CLK Rise Time tCLKR Max 2 5 1 92 1 852 ns CLK Fall Time tCLKF CLK High or Low Time tCLKH L Min 5 4 3 86 ns Internal Access Time tIA Max 75 72 34 ns Burst Access Time Valid Clock to Output D...

Page 50: ...urs before AVD is driven to Low 2 VA Valid Read Address RD Read Data Parameter Symbol Min Max Unit Access Time from CE Low tCE 80 ns Asynchronous Access Time from address valid tACC 80 Read Cycle Time...

Page 51: ...a Setup to rising edge of WE tDS 20 ns Data Hold from rising edge of WE tDH 0 ns CE Setup to falling edge of WE tCS 4 ns CE Hold from rising edge of WE tCH 0 ns WE Pulse Width tWP 25 ns WE Pulse Width...

Page 52: ...meter Description All Speed Options Unit JEDEC Std tRP RESET Pulse Width Min 50 ns tRH Reset High Time Before Read Min 200 ns tRPH RESET Low to CE Low Min 10 us OE CE AVD WE CLK VCC tAAVDS tWP tAAVDH...

Page 53: ...cycle before data CR 8 0 in the Configuration Register 3 Figure shows the device crossing a bank in the process of performing an erase or program CLK Address hex D124 D125 D126 D127 D128 D129 D130 sta...

Page 54: ...0000 initial data is valid on the Reserved rising CLK edge after addresses are latched 0001 3rd 0010 4th 0011 5th 0100 6th 0101 7th 0110 8th 0111 9th 1000 10th 1011 13th 1100 Reserved 1111 Data AVD O...

Page 55: ...ile checking the status of the program or erase operation in the busy bank The system should read status twice to ensure valid information OE CE WE tOEZ Data Addresses AVD WD 25h RA WA tWC tDS tDH tRC...

Page 56: ...polling rate as 400 ns 7 The erase time is calculated from the time of issuing erase command to the completion of erase operation indicated by status register Parameter Typ Note 1 Max Note 2 Unit Comm...

Page 57: ...d above the system address byte Table 43 Command Definitions Command Sequence Cycles Bus Cycles Notes 1 4 First Second Third Fourth Addr Data Addr Data Addr Data Addr Data Read RA RD Reset 1 X F0 Writ...

Page 58: ...0 Write Buffer Load 3 SA 555 SA AAA 25 SA 2AA SA 554 0 SA X00 PD Buffer to Flash Configuration Register 1 SA 555 SA AAA 29 Configuration Register Read 1 SA X00 RR Configuration Register Exit 1 XXX FO...

Page 59: ...est word address of the words being programmed within the 32 word write buffer page This is not necessarily the lowest address of the page Data words are loaded into the write page buffer in sequentia...

Page 60: ...Q15 DQ8 Reserved DQ7 Factory Lock Bit 1 Locked 0 Not Locked DQ6 Customer Lock Bit 1 Locked 0 Not locked DQ5 DQ0 Reserved Indicator Bits SA 08h SA 10h Reserved Reserved SA 09h SA 12h Reserved Reserved...

Page 61: ...voltage D7 D4 Volt D3 D0 100 millivolt SA 1Dh SA 3Ah 0085h VPP Programming Supply Minimum Program Erase voltage 00h no VPP pin present SA 1Eh SA 3Ch 0095h VPP Programming Supply Maximum Program Erase...

Page 62: ...se Block Region 1 information lower byte Number of Erase sectors of identical size within the Erase Block Region 00h 1 sector 01h 2 sectors 02h 3 sectors 03h 4 sectors 0003h Bottom Boot 0003h Bottom B...

Page 63: ...s in per group SA 48h SA 90h 0000h Sector Temporary Unprotect 00h Not Supported 01h Supported SA 49h SA 92h 0009h Sector Protect Unprotect scheme 08h Advanced Sector Protection 09h Single Sector Lock...

Page 64: ...mon Flash Interface SA 58h SA B0h 0020h Top Boot 0010h Top Boot Bank 0 Region Information X Number of sectors in bank 0023h Bottom Boot 0013h Bottom Boot SA 59h SA B2h 0020h 0010h Bank 1 Region Inform...

Page 65: ...hich AVD is Low and OE is High OE is ignored after OE returns high between accesses until the next Address Low is received OE low with AVD low signals the presence of Address High The Address High cyc...

Page 66: ...AVD OE WE A DQ15 A DQ0 RDY Add High Add Low Data tCEZ tCR tDH tDS tAAVDH tAAVDH tAAVDS tAAVDS tCH tVLWH tWC tWP tCS tWPH tWEA tAAVDH tAAVDS tAVDP tAVDP tAVDP tCAS OE low with AVD low signals the prese...

Page 67: ...H AL D tCEZ tCR tCEZ tOEZ tACC tACC tOE tDH tDS tAAVDH tAAVDS tOEH tVLWH tCH tWC tWP tCS tWPH tWEA tAVDO tAAVDH tAAVDS tAVDP tCAS CLK CE AVD OE WE A DQ15 A DQ0 RDY CLK may be at VIL or VIH or Active A...

Page 68: ...after OE returns high between accesses until the next Address Low is received OE low with AVD low signals the presence of Address High The Address High cycle is optional When the high part of address...

Page 69: ...ta out OE enables data output only after the Address Low cycle in which AVD is Low and OE is High OE is ignored after OE returns high between accesses until the next Address Low is received OE low wit...

Page 70: ...C tRACC tCR tOEZ tBACC tBDH tBACC tOE tDH tDS tACH tACS tCH tVLWH tWP tOEH tWC tWPH tWEA tAVDP tAVDH tAVDP tAVDS tCES tIA CLK CE AVD OE WE A DQ15 A DQ0 RDY with data RDY before data AH AL Write Data A...

Page 71: ...Figure 33 Synchronous Write Followed By Write AADM Interface AH AL Write Data AH AL Write Data tCEZ tRACC tRACC tRACC tCR tDH tDS tAAVDH tAAVDS tDH tDS tAAVDH tAAVDS tVLWH tCH tWP tVLWH tWC tWPH tWEA...

Page 72: ...Clarified some points Ordering Information and Valid Combinations Added Industrial Temperature range option Address Data Interface Corrected typo Device Bus Operations Table Corrected A DQ15 A DQ0 co...

Page 73: ...to OE H with relevant values Performance Characteristics Updated tables Erase and Programming Performance Changed typical programming times F WIOB 11 18 2010 Erase and Programming Performance Changed...

Page 74: ...dated VDJ044 44 Ball Very Thin Fine Pitch Ball Grid Array 6 2 mm x 7 7 mm Removed existing spec Added spec 002 24745 Updated to new template Completing Sunset Review Document History Page Continued Do...

Page 75: ...the application or use of any product or circuit described in this document Any information provided in this document including any sample design information or programming code is provided only for...

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