Document Number: 002-00833 Rev. *L
Page 22 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
7.2.3
Continuous Burst
The device continues to output sequential burst data from the memory array, wrapping around to address 0000000h after it reaches
the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new
address. See
Table 7, Device Bus Operations on page 14
If the host system crosses a bank boundary while reading in burst mode, and the subsequent bank is not programming or erasing,
an address boundary crossing latency might be required. If the host system crosses the bank boundary while the subsequent bank
is programming or erasing, continuous burst halts (RDY will be disabled and data will continue to be driven).
7.2.4
8-, 16-Word Linear Burst with Wrap Around
The remaining two modes are fixed length linear burst with wrap around, in which a fixed number of words are read from consecutive
addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls.
The groups are sized according to the number of words read in a single burst sequence for a given mode (see
As an example: if the starting address in the 8-word mode is system byte address 3Ch, the address range to be read would be byte
address 30-3Fh, and the burst sequence would be 3C-3E-30-32-34-36-38-3Ah. The burst sequence begins with the starting address
written to the device, wraps back to the first address in the selected group, and outputs a maximum of 8 words. No additional wait
states will be required within the 8-word burst. The 8th word will continue to be driven until the burst operation is aborted (CE# goes
to V
IH
, a new address is latched in for a new burst operation, or a hardware reset). In a similar fashion, the 16-word Linear Wrap
modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the
selected address group. Additional wait states could be added the first time the device crosses from one to the other group of 8
words in a 16-word burst. The number will depend on the starting address and the wait state set within the configuration register.
Note that in these two burst read modes the address pointer does not cross the boundary that occurs every 128 words;
thus, no 128-word address boundary crossing wait states are inserted for linear burst with wrap.
Table 19. Burst Address Groups
Mode
Group Size
Group Byte Address Ranges
8-word
16 bytes
0-Fh, 10-1Fh, 20-2Fh,...
16-word
32 bytes
0-1Fh, 20-3Fh, 30-4Fh,...
