Cypress S29VS128R Manual Download

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Document Number: 002-00833 Rev. *L

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S29VS256R
S29VS128R
S29XS256R
S29XS128R

By breaking up the memory address in to two time slots the address is naturally extended to be a 32-bit word address. But, using
two bus cycles to transfer the address increases initial access latency by increasing the time address is using the bus. However,
many memory accesses are to locations in memory nearby the previous access. Very often it is not necessary to provide both cycles
of address. This interface stores the high half of address in the memory so that if the high half of address does not change from the
previous access, only the low half of address needs to be sent on the bus. If a new upper address is not captured at the beginning of
an access the last captured value of the upper address is used. This allows accesses within the same 128-KByte address range to
provide only the lower address as part of each access.

In AADM mode two signal rising edges are needed to capture the upper and lower address portions in asynchronous mode or two
signal combinations over two clocks is needed in synchronous mode. In asynchronous mode the upper address is captured by an
AVD# rising edge when OE# is Low; the lower address is captured on the rising edge of AVD# with OE# High. In synchronous mode
the upper address is captured at the rising clock edge when AVD# and OE# are Low; the lower address is captured at the rising
edge of clock when AVD# is Low and OE# is High.

CE# going High at any time during the access or OE# returning High after RDY is first asserted High during an access, terminates
the read access and causes the address/data bus direction to switch back to input mode. The address/data bus direction switches
from input to output mode only after an Address-Low capture when AVD# is Low and OE# is High. This prevents the assertion of
OE# during Address-High capture from causing a bus conflict between the host address and memory data signals. Note, in burst
mode, this implies at least one cycle of CE# or OE# High before an Address-high for a new access may be placed on the bus so that
there is time for the memory to recognize the end of the previous access, stop driving data outputs, and ignore OE# so that assertion
of OE# with the new Address-high does not create a bus conflict with a new address being driven on the bus. At high bus
frequencies more than one cycle may be need in order to allow time for data outputs to stop driving and new address to be driven
(bus turn around time).

During a write access, the address/data bus direction is always in the input mode.

The upper address is set to Zero or all Ones, for bottom or top boot respectively, during a Hardware Reset, operate in ADM mode
during the early phase of boot code execution where only a single address cycle would be issued with the lower 16 bit of the address
reaching the memory in AADM mode. The default high order address bits will direct the early boot accesses to the 128 Kbytes at the
boot end of the device. Note that in AADM interface mode this effectively requires that one of the boot sectors is selected for any
address overlay mode because in the initial phase of AADM mode operation the host memory controller may only issue the low
order address thus limiting the early boot time address space to the 128 Kbytes at the boot end of the device.

6.3.3

Default Access Mode

Upon power-up or hardware reset, the device defaults to the Asynchronous Access mode.

6.4

Bus Operations

Table 7

describes the required state of each input signal for each bus operation.

Table 7. Device Bus Operations

Operation

CE#

OE#

WE#