Document Number: 002-00833 Rev. *L
Page 56 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
10.9.6
Erase and Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V
CC
, 10,000 cycles. Additionally, programming typically assumes a checkerboard
pattern.
2. Under worst case conditions of –25°C, V
CC
= 1.70 V, 100,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the bus-cycle sequence for the program command. See
for further information on
command definitions.
5. The device has a minimum erase and program cycle endurance of 10,000 cycles.
6. The first value excludes pre-programming time, while the second value is inclusive of pre-programming time for the FFFFh pattern, with status polling rate as 400 ns.
7. The erase time is calculated from the time of issuing erase command to the completion of erase operation (indicated by status register)
Parameter
Max
Unit
Comments
Sector Erase Time
128 Kbyte
V
CC
0.8/1.3
3.5/5.5
s
32 Kbyte
V
CC
0.35/0.6
2.0/3.5
128 Kbyte
V
PP
0.8/1.3
3.5/5.5
32 Kbyte
V
PP
0.35/0.6
2.0/3.5
,
V
CC
78/126 (128 Mbit)
155/251 (256 Mbit)
200/325 (128 Mbit)
400/650 (256 Mbit)
V
PP
78/126 (128 Mbit)
155/251 (256 Mbit)
154/250 (128 Mbit)
308/500 (256 Mbit)
Single Word Program Time (using
Program Buffer)
V
CC
170
800
µs
Excludes system level
overhead
Effective Word Programming Time
using Program Write Buffer
V
CC
14.1
94
V
PP
9
48
Total 32-Word Buffer Programming
Time
V
CC
450
3000
V
PP
288
1540
Chip Programming Time
(using 32 word buffer)
V
CC
118 (128 Mbit)
236 (256 Mbit)
157 (128 Mbit)
315 (256 Mbit)
s
Excludes system level
overhead
V
PP
76 (128 Mbit)
151 (256 Mbit)
80 (128 Mbit)
160 (256 Mbit)
Erase Suspend/Erase Resume (t
ESL
)
30
µs
Program Suspend/Program Resume
(t
PSL
)
30
µs
Blank Check
1
ms
