Canon CLBP-460PS, Service Manual

Page: 62 / 566

II. ENGINE CONTROL SYSTEM
A. DC Controller PCB
1. Outline
The operations of the printer are controlled by three CPUs (D-CPU, M-CPU, and S-CPU) on the
DC controller PCB.
The D-CPU (IC1001) controls the engine system and the video interface with the video con-
troller. The M-CPU (IC1009) controls various loads according to instructions from the D-CPU.
The S-CPU (IC1010) controls the developing cylinder of the toner cartridge according to instruc-
tions from the M-CPU.
The layout of the main ICs on this PCB is shown in Figure 2-2-1, and its block diagram, in
Figure 2-2-2.
2. Operations
a. D-CPU (IC1001)
The D-CPU is an eight-bit single-chip microcomputer (UPD78P058GC-8BIT).
This CPU is a single-chip CPU with built-in ROM and RAM. It controls the engine system,
video interface with the video controller, laser/scanner unit, fixing unit, and fans according to
the control program stored in the ROM via the gate array.
b. M-CPU (IC1009)
The M-CPU is an eight-bit single-chip microcomputer (CXP875P40Q-1).
This CPU is a single-chip CPU incorporating a ROM and a RAM. This CPU uses the control
program stored in the ROM to control various loads, such as motors, clutches, and solenoids,
and high-voltage. It also controls options, such as the duplexing unit and paper feeder.
c. S-CPU (IC1010)
The S-CPU is an four-bit single-chip microcomputer (M34225M1-XXXFP).
This CPU is a single-chip CPU incorporating a ROM and a RAM. This CPU uses the control
program stored in the ROM to control the toner cartridge motor.
d. Gate array (IC1003)
The gate array has the following main functions:
1) Laser/scanner control
2) Video interface control
3) Photointerrupter and sensor control
4) Switch control
5) Clock control
6) Image density control
e. RAM (IC1005)
This buffer memory stores the video signal (one line) from the video controller. The CLOCK sig-
nal (VCLK) of the video controller is converted to the CLOCK signal (PCLK) of the printer.
f. BD sync IC (IC1006)
The BD sync IC generates the PRINTER CLOCK signal (PCLK) based on the /BD signal from the
BD PCB.
g. Reset IC (IC1002)
The reset IC sends a HARDWARE RESET signal to the D-CPU and the gate array when the power
is turned ON.
2 - 4
CHAPTER 2