DL06 Micro PLC User Manual, 3rd Edition, Rev. E
3-15
Chapter 3: CPU Specifications and Operation
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WARNING: Only authorized personnel fully familiar with all aspects of the application should make
changes to the program. Make sure you thoroughly consider the impact of any changes to minimize
the risk of personal injury or damage to equipment.
CPU Bus Communication
It is possible to transfer data to and from the CPU over the CPU bus on the backplane. This
data is more than standard I/O point status. This type of communications can only occur on
the CPU (local) base. There is a portion of the execution cycle used to communicate with these
modules. The CPU performs both read and write requests during this segment.
Update Clock, Special Relays and Special Registers
The DL06 CPUs have an internal real-time clock and calendar timer which is accessible to the
application program. Special V-memory locations hold this information. This portion of the
execution cycle makes sure these locations get updated on every scan. Also, there are several
different Special Relays, such as diagnostic relays, for example, that are also updated during
this segment.
Input Update
Result of Program
Solution
OFF
Image Register (example)
Y1
Y2
...
Y128
ON
ON
...
OFF
C0
C1
C2
...
C377
OFF
OFF
ON
...
OFF
Y0
OFF
X1
X2
...
X128
ON
ON
...
OFF
X0
Bit Override OFF
Force from
Programmer
Input Update
Result of Program
Solution
Bit Override ON
Force from
Programmer
