Artesyn Centellis 2100 Shelf Release 3.0, Installation And Use Manual

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Non-Field-Replaceable Units
Centellis 2100 Shelf Release 3.0 Installation and Use (6806800T37D )
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5.1.3 Update Channel
The update channel connects the two node slots. It is comprised of 10 differential signal pairs
capable of bit rates up to 3.125 Gbits/s each in a point-to-point connection. For further details
refer to the
PICMG 3.0 R3.0 specification . The blades may use those lines for their proprietary
purpose.
The update channel is fully compliant to the PICMG 3.0 R3.0 Specification . Therefore, details are
not described within this chapter. For more information, see the PICMG 3.0 R3.0 Specification .
5.1.4 Synchronization Clock Interface
The complete synchronization clock interface is bussed between the user card and node slots.
It provides a set of clock buses to support applications that require the exchange of
synchronous timing information among multiple boards in a shelf. The synchronization clock
interface path is:
terminator – node slot 1 – user card slot 1 – user card slot 2 – node slot 2 – terminator.
The termination resistors are mounted on the backplane.
The synchronization clock interface is fully compliant to the PICMG 3.0 R3.0 Specification .
Therefore, details are not described within this chapter. For more information, see the PICMG
3.0 R3.0 Specification .
5.2 Alarm Panel
The alarm panel is located on the front of the shelf. It provides LEDs for the following alarm
states of the system:
The signaling is controlled by the system manager via commands via ATCA-MF106. The alarm
states are controlled by the system manager.
Alarm State LED Color
Minor AMBER
Major RED
Critical RED