AT32F421
Series Reference Manual
2022.11.11
Page 87
Rev 2.02
6.2.10 Peripheral multiplexed function configuration
When IOMUX multiplexed function is needed:
To use a peripheral pin as a multiplexed output, the corresponding pin should be configured as
multiplexed push-pull/open-drain output.
To use a peripheral pin as a MUX input, the corresponding pin configured as floating input/pull-
up/pull-down input.
For ADC peripherals, the pin corresponding to analog channel should be configured as analog
input/output mode.
For I2C peripherals that intend to use a pins as bidirectional function, the corresponding pin should
be configured as open-drain mode.
6.2.11 IOMUX map priority
Almost all peripherals can be configured as corresponding multiplexed functions using GPIOx_MUXL or
GPIOx_MUXH registers, except for a few pins that might be occupied by hardware directly.
Some of the pins, no matter whatever GPIO mode configuration, are always owned by specific hardware
feature directly.
Table 6-4 Hardware preemption
Pin
Enable bit
Description
PA0
PWC_CTRLSTS[8] =1
Once enabled, PA0 pin acts as WKUP1
function of PWC.
PB5 PWC_CTRLSTS[13] =1
Once enabled, PB5 pin acts as WKUP6
function of PWC
PB15 PWC_CTRLSTS[14] =1
Once enabled, PB15 pin acts as WKUP7
function of PWC
PC13
PWC_CTRLSTS[9] = 1
Once enabled, PA0 pin acts as WKUP2
function of PWC
PC13
(ERTC_CTRL[23:21] !=3’b000)|(ERTC_CTRL[11] !=0)|
(ERTC_TAMP[0] != 0)
Once enabled, PC13 pin acts as RTC
channel input/output
PC14
CMR_BPDC[0]=1
Once enabled, PC14 pin acts as LEXT
channel
PC15
CMR_BPDC[0]=1
Once enabled, PC15 pin acts as LEXT
channel
PF0
CMR_CTRL[16]=1
Once enabled, PF0 pin acts as HEXT
channel
PF1
CMR_CTRL[16]=1
Once enabled, PF1 pin acts as HEXT
channel
6.2.12 External interrupt/wake-up lines
Each pin can be used as an external interrupt input and thus the corresponding pin must be configured
as input mode.
6.3 GPIO registers
lists GPIO register map and their reset values. These peripheral registers must be
accessed by bytes (8-bit), half-words (16-bit) or words (32 bits).
Table 6-5 GPIO register map and reset value s
Register
Offset
Reset value
GPIOA_CFGR
0x00
0x2800 0000
GPIOx_CFGR(x = B,C,F)
0x00
0x0000 0000
GPIOx_OMODE
0x04
0x0000 0000
GPIOA_ODRVR
0x08
0x0C00 0000
GPIOx_ODRVR(x = B,C,F)
0x08
0x0000 0000