AT32F421
Series Reference Manual
2022.11.11
Page 193
Rev 2.02
TMR3_PR
0x2C
0x0000 0000
TMR3_C1DT
0x34
0x0000 0000
TMR3_C2DT
0x38
0x0000 0000
TMR3_C3DT
0x3C
0x0000 0000
TMR3_C4DT
0x40
0x0000 0000
TMR3_DMACTRL
0x48
0x0000
TMR3_DMADT
0x4C
0x0000
14.2.4.1 Control register1 (TMR3_CTRL1)
Bit
Register
Reset value
Type
Description
Bit 15: 10
Reserved
0x00
resd
Kept at its default value
Bit 9: 8
CLKDIV
0x0
rw
Clock divider
00: Normal
01: Divided by 2
10: Divided by 4
11: Reserved
Bit 7
PRBEN
0x0
rw
Period buffer enable
0: Period buffer is disabled
1: Period buffer is enabled
Bit 6: 5
TWCMSEL
0x0
rw
Two-way counting mode selection
00: One-way counting mode, depending on the
OWCDIR bit
01: Two-way counting mode1, count up and down
alternately, the output flag bit is set only when the counter
counts down
10: Two-way counting mode2, count up and down
alternately, the output flag bit is set only when the counter
counts up
11: Two-way counting mode3, count up and down
alternately, the output flag bit is set when the counter
counts up / down
Bit 4
OWCDIR
0x0
rw
One-way count direction
0: Up
1: Down
Bit 3
OCMEN
0x0
rw
One cycle mode enable
This bit is use to select whether to stop counting at an
overflow event
0: The counter does not stop at an overflow event
1: The counter stops at an overflow event
Bit 2
OVFS
0x0
rw
Overflow event source
This bit is used to select overflow event or DMA request
sources.
0: Counter overflow, setting the OVFSWTR bit or
overflow event generated by slave timer controller
1: Only counter overflow generates an overflow event
Bit 1
OVFEN
0x0
rw
Overflow event enable
0: Enabled
1: Disabled
Bit 0
TMREN
0x0
rw
TMR enable
0: Enabled
1: Disabled