AT32F421
Series Reference Manual
2022.11.11
Page 252
Rev 2.02
14.5.4.7 TMR16 and TMR17 channel control register (TMRx _CCTRL)
Bit
Register
Reset value
Type
Description
Bit 15: 4
Reserved
0x0
resd
Kept its default value.
Bit 3
C1CP
0x0
rw
Channel 1 complementary polarity
0: C1COUT is active high.
1: C1COUT is active low.
Bit 2
C1CEN
0x0
rw
Channel 1 complementary enable
0: Output is disabled.
1: Output is enabled.
Bit 1
C1P
0x0
rw
Channel 1 polarity
When the channel 1 is configured as output mode:
0: C1OUT is active high
1: C1OUT is active low
When the channel 1 is configured as input mode:
00: C1IN is active on its rising edge. When used as
external trigger, C1IN is not inverted.
01: C1IN is active on its falling edge. When used as
external trigger, C1IN is inverted.
10: Reserved
11: C1IN is active on the rising edge and falling edge.
When used as external trigger, C1IN is not inverted.
Bit 0
C1EN
0x0
rw
Channel 1 enable
0: Input or output is disabled
1: Input or output is enabled
Table 14-13 Complementary output channel CxOUT and CxCOUT control bits with
brake function
Control bit
Output state
(1)
OEN bit
FCSODIS
bit
FCSOEN
bit
CxEN
bit
CxCEN
bit
CxOUT output state
CxCOUT output state
1
X
0
0
0
Output disabled
(no driven by the timer)
CxOUT=0, Cx_EN=0
Output disabled
(no driven by the timer)
CxCOUT=0, CxCEN=0
0
0
1
Output disabled
(no driven by the timer)
CxOUT=0, Cx_EN=0
polarity,
CxCOUT= CxORAW xor
CxCP, CxCEN=1
0
1
0
polarity
CxOUT= CxORAW xor CxP,
Cx_EN=1
Output disabled
(no driven by the timer)
CxCOUT=0, CxCEN=0
0
1
1
pdead-
time,
Cx_EN=1
CxORAW
ipdead-
time,
CxCEN=1
1
0
0
Output disabled
(no driven by the timer)
CxOUT=CxP, Cx_EN=0
Output disabled
(no driven by the timer)
CxCOUT=CxCP,
CxCEN=0
1
0
1
Off-state
(Output enabled with
inactive level)
CxOUT=CxP, Cx_EN=1
polarity,
CxCOUT= CxORAW xor
CxCP, CxCEN=1
1
1
0
polarity,
CxOUT= CxORAW xor CxP,
Cx_EN=1
Off-state
(Output enabled with
inactive level)
CxCOUT=CxCP,
CxCEN=1
1
1
1
pdead-
time, Cx_EN=1
CxORAW
ipdead-
time,
CxCEN=1