AT32F421
Series Reference Manual
2022.11.11
Page 180
Rev 2.02
Figure 14-13 Counting in external clock mode B, with PR=0x32 and DIV=0x0
30
COUNTER
OVFIF
TMR_CLK
00
ESDIV[1:0]
Clear
CK_CNT
EXT
0000
ESF[3:0]
31
32
0
1
2
3
4
Internal trigger input (ISx)
Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can
be provided by the TRGOUT signal output by another timer. Set the STIS[2: 0] bit to select internal
trigger signal to enable counting.
The TMR3 timer consists of a 16-bit prescaler, which is used to generate the CK_CNT that enables the
counter to count. The frequency division relationship between the CK_CNT and TMR_CLK can be
adjusted by setting the value of the TMR3_DIV register. The prescaler value can be modified at any time,
but it takes effect only when the next overflow event occurs.
The internal trigger input configuration process is as follows:
Set the TMRx_PR register to set counting period.
Set the TMRx_DIV register to set counting frequency.
Set the TWCMSEL[1:0] bit in the TMRx_CTRL1 register to set counting mode.
Set
the STIS[2:0] bit (range: 3’b000~3’b011) in the TMRx_STCTRL register to select internal
trigger.
Set
SMSEL[2:0]=3’b111 in the TMRx_STCTRL register to select external clock mode A.
Set the TMREN bit in the TMRx_CTRL1 register to enable TMRx counter.
Table 14-3 TMR3 internal trigger connection
Slave timer
IS0
(STIS = 000)
IS1
(STIS = 001)
IS2
(STIS = 010)
IS3
(STIS = 011)
TMR3
TMR1
-
TMR15
-
Note 1: If there is no corresponding timer in a device, the corresponding trigger signal ISx is not present.
Figure 14-14 Counter timing with prescaler value changing from 1 to 4
TMR_CLK
CK_CNT
COUNTER
OVFIF
DIV[15
:
0]
18
17
19
1A
1B
1C
0
3
00
01
Clear
PR[15
:
0]
1C