AT32F421
Series Reference Manual
2022.11.11
Page 169
Rev 2.02
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I
2
S mode)
Bit
Register
Reset value
Type
Description
Bit 15: 0
RCRC
0x0000
ro
Receive CRC
When CRC calculation is enabled, this register contains
the CRC value computed based on the received data.
This register is reset when the CCEN bit in the
SPI_CTRL1 register is cleared.
When the data frame format is set to 8-bit data, only the
8-bit LSB ([7: 0]) are calculated based on CRC8 standard;
when 16-bit data bit is selected, follow CRC16 standard.
Note: This register is only used in SPI mode.
13.4.7 SPITxCRC register (SPI_TCRC)
Bit
Register
Reset value
Type
Description
Bit 15: 0
TCRC
0x0000
ro
Transmit CRC
When CRC calculation is enabled, this register contains
the CRC value computed based on the transmitted data.
This register is reset when the CCEN bit in the
SPI_CTRL1 register is cleared.
When the data frame format is set to 8-bit data, only the
8-bit LSB ([7: 0]) are calculated based on CRC8 standard;
when 16-bit data bit is selected, follow CRC16 standard.
Note: This register is only used in SPI mode.
13.4.8 SPI_I2S configuration register (SPI_I2SCTRL)
Bit
Register
Reset value
Type
Description
Bit 15: 12 Reserved
0x0
resd
Forced to be 0 by hardware.
Bit 11
I2SMSEL
0x0
rw
I
2
S mode select
0: SPI mode
1: I
2
S mode
Bit 10
I2SEN
0x0
rw
I
2
S enable
0: Disabled
1: Enabled
Bit 9: 8
OPERSEL
0x0
rw
I
2
S operation mode select
00: Slave transmission
01: Slave reception
10: Master transmission
11: Master reception
Bit 7
PCMFSSEL
0x0
rw
PCM frame synchronization
This bit is valid only when the PCM standard is used.
0: Short frame synchronization
1: Long frame synchronization
Bit 6
Reserved
0x0
resd
Kept at its default value
Bit 5: 4
STDSEL
0x0
rw
I
2
S standard select
00: Philips standard
01: MSB-aligned standard (left-aligned)
10: LSB-aligned standard (right-aligned)
11: PCM standard
Bit 3
I2SCLKPOL
0x0
rw
I
2
S clock polarity
This bit indicates the clock polarity on the clock pin in idle
state.
0: Low
1: High
Bit 2: 1
I2SDBN
0x0
rw
I
2
S data bit num