AT32F421
Series Reference Manual
2022.11.11
Page 57
Rev 2.02
Bit 27
PORRSTF
0x1
ro
POR/LVR reset flag
Set by hardware. Cleared by writing to the RSTFC bit.
0: No POR/LVR reset occurs
1: POR/LVR reset occurs.
Bit 26
NRSTF
0x1
ro
NRST pin reset flag
Set by hardware. Cleared by writing to the RSTFC bit.
0: No NRST pin reset occurs
1: NRST pin reset occurs
Bit 25
Reserved
0x0
resd
Kept at its default value.
Bit 24
RSTFC
0x0
rw
Reset flag clear
Cleared by writing 1 through software.
0: No effect
1: Clear the reset flag.
Bit 23: 2 Reserved
0x000000
resd
Kept at its default value.
Bit 1
LICKSTBL
0x0
ro
LICK stable
0: LICK is not ready.
1: LICK is ready.
Bit 0
LICKEN
0x0
rw
LICK enable
0: Disabled
1: Enabled
4.3.11 AHB peripheral reset register (CRM_AHBRST)
Access: 0 wait state, accessible by words, half-words and bytes.
Bit
Name
Reset value
Type
Description
Bit 31:23
Reserved
0x000
resd
Kept at its default value.
Bit 22
GPIOFRST
0x0
rw
GPIOF reset
This bit is set or cleared by software.
0: Does not reset GPIOF
1: Reset GPIOF
Bit 21: 20 Reserved
0x000
resd
Kept at its default value.
Bit 19
GPIOCRST
0x0
rw
GPIOC reset
This bit is set or cleared by software.
0: Does not reset GPIOC
1: Reset GPIOC
Bit 18
GPIOBRST
0x0
rw
GPIOB reset
This bit is set or cleared by software.
0: Does not reset GPIOB
1: Reset GPIOB
Bit 17
GPIOARST
0x0
rw
GPIOA reset
This bit is set or cleared by software.
0: Does not reset GPIOA
1: Reset GPIOA
Bit 16: 0
Reserved
0x00000
resd
Kept at its default value.
4.3.12 PLL configuration register (CRM_PLL)
Bit
Name
Reset value
Type
Description
Bit 31
PLLCFGEN
0x0
rw
PLL configuration enable
0: Common integer multiplication mode, which is done
by PLL_FREF and PLLMULT registers.
1: Flexible configuration mode, which is done by
P
LL_MS/PLL_NS/PLL_FR registers.
Bit 30: 27 Reserved
0x0
resd
Kept at its default value.
Bit 26: 24 PLL_FREF
0x0
rw
PLL input clock selection
This field is valid only if PLLCFGEN=0.
000: 3.9 ~ 5 MHz
001: 5.2 ~ 6.25 MHz
010: 7.8125 ~ 8.33 MHz
011: 8.33 ~ 12.5 MHz
100: 15.625 ~ 20.83 MHz
101
:
20.83 ~ 31.25 MHz
110: Reserved
111: Reserved
Bit 23: 17 Reserved
0x00
resd
Kept at its default value.