AT32F421
Series Reference Manual
2022.11.11
Page 152
Rev 2.02
13.2.3 Chip select controller
The Chip select controller (CS) is used to enable hardware or software control for chip select signals
through software configuration. This controller is used to select master/slave device in multi-processor
mode, and to avoid conflicts on the data lines by first enabling the SCK signal and then CS signal. The
hardware and software configuration procedure is detailed as follows, along with their respective
input/output in master and slave mode.
CS hardware configuration procedure:
In master mode with CS being as an output, HWCSOE=1, SWCSEN=0, the CS hardware control is
enabled. If the SPI is enabled, low level is output on the CS pin. The CS signal is then released after the
SPI is disabled and the transmission is complete.
In master mode with CS being as an input, HWCSOE=0, SWCSEN=0, the CS hardware control is
enabled. At this point, the SPI is automatically disabled by hardware and enters slave mode as soon as
the CS pin low is detected by master SPI. The mode error flag (MMERR bit) is set at the same time. An
interrupt is generated if ERRIE=1. When the MMERR is set, the SPIEN and MSTEN cannot be set by
software. The MMERR is cleared by read or write access to the SPI_STS register followed by write
operation to the SPI_CTRL1 register.
In slave mode with CS being as an input, HWCSOE=0, SWCSEN=0, the CS hardware control is enabled.
The slave selects whether to transmit / receive data based on the level on the CS pin. The slave is
selected for data reception and transmission only when the CS pin is low.
CS software configuration procedure:
In master mode with CS being as an input, SWCSEN=1, the CS software control is enabled. When
SWCSIL=0, the SPI is automatically disabled by hardware and enters slave mode. The mode error flag
(MMERR bit) is set at this time. An interrupt is generated if ERRIE=1. When the MMERR bit is set, the
SPIEN and MSTEN bits cannot be set by software. The MMERR bit is cleared by read or write access
to the SPI_STS register followed by write operation to the SPI_CTRL1 register.
In slave mode with CS being as an input, SWCSEN=1, the CS software control is enabled. The SPI
judges the CS signal with the SWCSIL bit, instead of CS pin. When SWCSIL=0, the slave is selected for
data reception and transmission.
13.2.4 SPI_SCK controller
The SPI protocol adopts synchronous transmission. In master mode and with the SPI being used as SPI,
it is required to generate a communication clock for data reception and transmission on the SPI, and the
communication clock should be output to the slave via IO for data reception and transmission. In slave
mode, the communication clock is provided by peripherals, and is input to the SPI via IO. In all, the
SPI_SCK controller is used for the generation and distribution of SPI_SCK, with the configuration
procedure detailed as follows:
SPI_SCK controller configuration procedure:
Clock polarity and clock phase selection: It is selected by setting the CLKPOL and CLKPHA bit.
Clock prescaler selection: Select the desired PCLK frequency by setting the CRM bit. Select the
desired prescaler by setting the MDIV[3: 0] bit.
Master/slave selection: Select SPI as master or slave by setting the MSTEN bit.
Note that the clock output is activated after the SPI is enabled in master reception-only mode, and it
remains output until when the SPI is disabled and the reception is complete.
13.2.5 CRC
There is an independent transmission and reception CRC calculation unit in the SPI. When used as SPI
through software configuration, the SPI enables CRC calculation and CRC check automatically while
the user is reading or writing through DMA or CPU. During the transmission, if the received data is not
consistent with, detected by hardware, the data in the SPI_RCRC register, and such data is exactly the
CRC value, then the CCERR bit will be set. An interrupt is generated if ERRIE=1.
The CRC function and configuration procedure of the SPI are described as follows.
CRC configuration procedure