AT32F421
Series Reference Manual
2022.11.11
Page 264
Rev 2.02
Count on both C1IN and
C2IN
High
Down
Up
Up
Down
Low
Up
Down
Down
Up
Figure 14-106 Example of encoder interface mode C
20
21
22
23
24
25
26
27
26
25
24
23
22
21
20
1F
COUNTER
0x3
TWCMSEL
[1:0]
CI1RAW
CI2RAW
UP
DOWN
14.6.3.3 TMR input function
The TMR1 has four independent channels. Each channel can be configured as input or output.
As input, each channel input signal is processed as below:
–
TMRx_CHx outputs the pre-processed CxIRAW. Set the C1INSEL bit to select the source of
C1IRAW from TMRx_CH1 or the XOR-ed TMRx_CH1, TMRx_CH2 and TMRx_CH3, and the
sources of C2IRAW, C3IRAW and C4IRAW are TMRx_CH2, TMRx_CH3 and TMRx_CH4,
respectively.
–
CxIRAW inputs digital filter and outputs a filtered signal CxIF. Set the sampling frequency and
sampling times of digital filter by setting the CxDF bit.
–
CxIF inputs edge detector and outputs the signal CxIFPx after edge selection. The edge selection
is controlled by CxP and CxCP bits, and can be selected as rising edge, falling edge or both edges
active.
–
CxIFPx inputs capture signal selector and then outputs the signal CxIN after setection. The capture
signal selector is controlled by the CxC bits. The source of CxIN can be set as CxIFPx, CyIFPx or
STCI. The CyIFPx (
x≠y) is the CyIFPy from channel y and handled by channel x edge detector (for
example, the C1IFP2 is the C1IFP1 from channel 1 and then handled by channel 2 edge detector),
and STCI derives from the slave timer controller, and its source is selected by setting the STIS bit.
–
CxIN outputs the signal CxIPS that is divided by the input channel divider. The division factor is set
to “No division”, “divided by 2”, “divided by 4” or “divided by 8” by setting the CxIDIV bit.
Figure 14-107
Input/output channel 1 main circuit
Capture
CNT counter
C1DT
Compare
C1DT
preload
0
1
C1OBEN
C1DT_shadow
C1OCTRL
Overflow event
DTC
Dead time
C1ORAW
1
0
C1EN
1
0
0
1
disable
C1P
FCSOEN
OEN
1
0
C1CEN
1
0
0
1
disable
C1CP
FCSOEN
OEN
XOR
C1P/C1CP
edge detector
C1IN
TMRx_CH2
TMRx_CH3
TMRx_CH1
C1INSEL
C1IRAW
filter
C1DF
C1IFP1
C2IFP1
STCI
C1C
C1IDIV
input divider
Capture trigger
C1P
polarity select
C1CP
polarity select
BRK
BRK
C1OUT
C1COUT
to GPIO
to GPIO
0
1
disable
frozen
state
0
1
0
1
C1IOS
FCSODIS
0
1
disable
frozen
state
0
1
0
1
C1CIOS
FCSODIS
C1EN