AT32F421
Series Reference Manual
2022.11.11
Page 135
Rev 2.02
Figure 12-6 Mute mode using Idle line or Address mark detection
RX pin
RDBF
frame0
frame1
Idle line detection(WUM = 0)
:
...
RM
Idle
frame5
frame2 3 4
Mute mode
Normal mode
RX pin
RM
ADDR=0
frame0
Address mark detection(WUM = 1)
:
Idle
ADDR=1
Mute mode
Normal mode
Idle
...
frame1 2 3 4
...
Matching
Address
6.
Synchronous mode:
By setting the CLKEN bit to 1, synchronous mode and clock pin output are enabled. Select CK pin
high or low in idle state by setting the CLKPOL bit (1 or 0). Whether to sample data on the second
or the first edge of the clock depends on the CLKPHA bit (1 or 0). The LBCP bit (1 or 0) is used to
select whether to output clock on the last data bit. And the ISDIV[4: 0] is used to select the required
clock output frequency.
Figure 12-7 8-bit format USART synchronous mode
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Stop
bit
Start
bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Start
bit
TX pin
RX pin
Stop
bit
CK pin
(CLKPOL=0
CLKPHA=0)
CK pin
(CLKPOL=1
CLKPHA=0)
CK pin
(CLKPOL=0
CLKPHA=1)
CK pin
(CLKPOL=1
CLKPHA=1)