AT32F421
Series Reference Manual
2022.11.11
Page 246
Rev 2.02
Figure 14-89 TMR output control
CxOUT(to GPIO)
holistic-out
enable state
CxEN
run state
frozen state
disable CxOUT
FCSOEN
0
1
1
0
holistic-out
disable state
active state
inactive state
state select
1
0
XOR
XOR
AND
CxIOS
CxP
CxCOUT(to GPIO)
1
0
holistic-out
enable state
CxCEN
frozen state
run state
1
0
holistic-out
disable state
state select
0
1
active state
CxCP
inactive state
CxCIOS
disable CxCOUT
FCSOEN
0
1
BRK
Clock failure event
From clock control CSS(Clock Security System)
OR
BRKV
polarity selection
BRKEN
break
trigger
break enable
OEN
break
event
AND
overflow event
AOEN
auto enable
CxCP
polarity select
CxP
polarity select
DTC(
dead time
)
CxORAW
OR
BRKEN
break
trigger
break enable
OEN
break
event
AND
overflow event
AOEN
auto enable
BRK
TMRx_BRK
BRKV
polarity selection
Clock failure event
From clock control CSS(Clock Security System)
1
0
GPIO output enable
TMRx_BRK
1
0
OR
AND
0
1
AND
OR
FCSODIS
CxCEN
CxEN
OR
AND
FCSOEN
FCSOEN
CxCE
GPIO output enable
TMR_CHx
TMR_CHxC
Figure 14-90 Example of TMR brake function
CxORAW
Delay
Delay
Delay
CxEN
CxCEN
CxIOS
CxCIOS
CxCOUT
CxOUT
BRK
AOEN
14.5.3.6 Debug mode
When the microcontroller enters debug mode (Cortex
TM
-M4 core halted), the TMRx counter stops
counting by setting the TMRx_PAUSE in the DEBUG module.
14.5.4 TMR16 and TMR17 registers
These peripheral registers must be accessed by word (32 bits).
TMR16 and TMR17 register are mapped into a 16-bit addressable space.
Table 14-12 TMR16 and TMR17 register map and reset value
Register
Offset
Reset value
TMRx_CTRL1
0x00
0x0000
TMRx_CTRL2
0x04
0x0000