Programmer’s Model
ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
3-5
Figure 3-2 Mailbox0 register map
Figure 3-3 shows the register map for each Interrupt0.
Figure 3-3 Interrupt0 register map
Mailbox Source Registers
0x000
Mailbox Destination Set Registers
Mailbox Destination Clear Registers
0x004
0x00C
0x008
Mailbox Destination Status Registers
Mailbox Mode Registers
0x010
Mailbox Mask Set Registers
Mailbox Mask Clear Registers
0x014
0x01C
0x018
Mailbox Mask Status Registers
Mailbox Send Registers
0x020
Mailbox Data Register 0
Mailbox Data Register 1
0x024
0x02C
0x028
Mailbox Data Register 2
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
0x030
0x034
0x03C
0x038
Masked Interrupt Status Registers
0x800
Raw Interrupt Status Registers
0x804
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