Functional Overview
2-16
Copyright © 2003, 2004. ARM Limited. All rights reserved.
ARM DDI 0306B
Number of data registers in each mailbox
Program the number of active data registers in each mailbox by tying off
the
DATANUM
input bus (Table 2-4).
Note
Any setting of
DATANUM
other than the values shown in Table 2-4 is
unsupported.
Usage constraints
There are several valid use models for a mailbox and some constraints under which they
can be used. Messages can be sent to:
Multiple cores
If a message is sent to multiple cores, you must use the Auto
Acknowledge feature and data must not be modified for the
acknowledge. Destination cores must clear their interrupts by
writing their Channel ID to the Destination Clear Register.
Single core
If there is only a single destination core, the Auto Acknowledge
mode is optional. If you disable the Auto Acknowledge mode, the
acknowledge is optional, although an acknowledge normally
happens, and the Mailbox Data Register can optionally be
updated. When Auto Acknowledge is disabled, the destination
core must clear its interrupt by clearing bit 0 of the Mailbox Send
Register.
Table 2-4 Configuring number of data registers
Number of
mailboxes
DATANUM
0
3’b000
1
3'b001
2
3'b010
3
3'b011
4
3'b100
5
3'b101
6
3'b110
7
3'b111
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