Functional Overview
2-12
Copyright © 2003, 2004. ARM Limited. All rights reserved.
ARM DDI 0306B
Multiple mailboxes are grouped together as shown in Figure 2-4 on page 2-11 to form
the 32-bit IPCM interrupt bus,
IPCMINT[31:0]
. All the interrupt bits from each
mailbox relating to a single Channel ID are grouped together to form the masked
interrupt status buses,
IPCMMIS0[31:0]
to
IPCMMIS31[31:0]
. The bits within these
buses are then ORed together to form the IPCM interrupt bus,
IPCMINT[31:0]
.
Configuration Status Register
The three configurable parameters for the IPCM are:
•
number of mailboxes, 1-32
•
number of data registers per mailbox, 0-7
•
number of interrupts, 1-32.
The configuration options that you choose define the read-only Configuration Status
Register, enabling software to determine the IPCM configuration by reading this
register. This enables a generic IPCM software driver to determine how to use each
IPCM instance within a system.
To define the IPCM configuration, tie off the
MBOXNUM
,
INTNUM
, and
DATANUM
input pins as follows:
Number of mailboxes
Program the number of active mailboxes by tying off the
MBOXNUM
input bus (Table 2-2).
Table 2-2 Configuring number of mailboxes
Number of
mailboxes
MBOXNUM
1
6'b000001
2
6'b000010
3
6'b000011
4
6'b000100
5
6'b000101
6
6'b000110
7
6'b000111
8
6'b001000
9
6'b001001
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