Programmer’s Model
3-8
Copyright © 2003, 2004. ARM Limited. All rights reserved.
ARM DDI 0306B
-
0x4C0-0x4
FC
-
-
Reserved for Mailbox19
-
0x500-0x5
3C
-
-
Reserved for Mailbox20
-
0x540-0x5
7C
-
-
Reserved for Mailbox21
-
0x580-0x5
BC
-
-
Reserved for Mailbox22
-
0x5C0-0x5
FC
-
-
Reserved for Mailbox23
-
0x600-0x6
3C
-
-
Reserved for Mailbox24
-
0x640-0x6
7C
-
-
Reserved for Mailbox25
-
0x680-0x6
BC
-
-
Reserved for Mailbox26
-
0x6C0-0x6
FC
-
-
Reserved for Mailbox27
-
0x700-0x7
3C
-
-
Reserved for Mailbox28
-
0x740-0x7
7C
-
-
Reserved for Mailbox29
-
0x780-0x7
BC
-
-
Reserved for Mailbox30
-
0x7C0-0x7
FC
-
-
Reserved for Mailbox31
IPCMMIS0
0x800
RO
0x00000000
See
Masked Interrupt Status Registers
on page 3-17
IPCMRIS0
0x804
RO
0x00000000
See
Raw Interrupt Status Registers
on page 3-18
-
0x808-0x8
0C
-
-
Reserved for Interrupt1
Table 3-1 IPCM register summary (continued)
Name
Base
offset
Type
Reset
value
Description
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