Functional Overview
ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
2-11
In Figure 2-4, each mailbox contains up to seven data registers to hold the message.
Every mailbox instance with a single IPCM must have the same number of data
registers.
Figure 2-4 Mailbox interrupt mapping to IPCM interrupt outputs
Each mailbox can generate up to 32 interrupts, one for each Channel ID. The number
of interrupts defines the number of bits in the Mailbox Source Register, Mailbox
Destination Register, and Mailbox Mask Register. For example, in Figure 2-4, the
IPCM has 32 interrupt outputs. Mailbox0 generates bit 0 of the
IPCMMIS0-31
buses,
while Mailbox31 generates bit 31 of the
IPCMMIS0-31
buses.
31
Source
0
31
Destination
0
31
Mask
0
Mode
Data0
Send
Data6
Mailbox31
IPCMMIS31[31]
IPCMMIS0[31]
31
Source
0
31
Destination
0
31
Mask
0
Mode
Data0
Send
Data6
Mailbox0
IPCMMIS31[0]
IPCMMIS0[0]
IPCMINT[31]
IPCMINT[0]
IPCMMIS31[31:0]
IPCMMIS0[31:0]
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from