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Glossary

ARM DDI 0306B

Copyright © 2003, 2004. ARM Limited. All rights reserved.

Glossary-3

Processor

A processor is the circuitry in a computer system required to process data using the
computer instructions. It is an abbreviation of microprocessor. A clock source, power
supplies, and main memory are also required to create a minimum complete working
computer system.

Reserved

A field in a control register or instruction format is reserved if the field is to be defined
by the implementation, or produces Unpredictable results if the contents of the field are
not zero. These fields are reserved for use in future extensions of the architecture or are
implementation-specific. All reserved bits not used by the implementation must be
written as 0 and read as 0.

Unpredictable

For reads, the data returned when reading from this location is unpredictable. It can have
any value. For writes, writing to this location causes unpredictable behavior, or an
unpredictable change in device configuration. Unpredictable instructions must not halt
or hang the processor, or any part of the system.

Word

A 32-bit data item.

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Summary of Contents for PrimeCelL PL320

Page 1: ...Copyright 2003 2004 ARM Limited All rights reserved ARM DDI 0306B PrimeCell Inter Processor Communications Module PL320 Revision r0p0 Technical Reference Manual Downloaded from Arrow com ...

Page 2: ... All particulars of the product and its use contained in this document are given by ARM Limited in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising fr...

Page 3: ...1 1 About the IPCM 1 2 Chapter 2 Functional Overview 2 1 Functional description 2 2 2 2 Functional operation 2 4 2 3 Examples of messaging 2 18 Chapter 3 Programmer s Model 3 1 About the programmer s model 3 2 3 2 Register summary 3 6 3 3 Register descriptions 3 12 Chapter 4 Programmer s Model for Test 4 1 Scan testing 4 2 4 2 Test registers 4 3 Downloaded from Arrow com Downloaded from Arrow com ...

Page 4: ... Limited All rights reserved ARM DDI 0306B Appendix A Signal Descriptions A 1 AMBA AHB signals A 2 A 2 Non AMBA signals A 3 Glossary Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 5: ...s 3 13 Table 3 5 IPCMxDSTATUS Register bit assignments 3 13 Table 3 6 IPCMxMODE Register bit assignments 3 14 Table 3 7 IPCMxMSET Register bit assignments 3 15 Table 3 8 IPCMxMCLEAR Register bit assignments 3 15 Table 3 9 IPCMxMSTATUS Register bit assignments 3 16 Table 3 10 IPCMxSEND Register bit assignments 3 17 Table 3 11 IPCMxDR0 6 Register bit assignments 3 17 Table 3 12 IPCMMISx Register bit...

Page 6: ...lID2 Register bit assignments 3 23 Table 3 22 IPCMPCellID3 Register bit assignments 3 23 Table 4 1 IPCMTCR Register bit assignments 4 3 Table 4 2 IPCMTOR Register bit assignments 4 3 Table A 1 AMBA AHB common signals A 2 Table A 2 AMBA AHB slave signals A 2 Table A 3 IPCM configuration signals A 3 Table A 4 IPCM interrupt signals A 3 Table A 5 Scan test signals A 3 Downloaded from Arrow com Downlo...

Page 7: ...ing from Core0 to Core1 2 21 Figure 2 9 Configuration messaging from Core0 to Cores 1 2 and 3 using Auto Acknowledge 2 22 Figure 2 10 Messaging from Core0 to Cores 1 2 and 3 using Auto Acknowledge 2 23 Figure 2 11 Configuration Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1 2 25 Figure 2 12 Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1 2 25 Figure 3 1 IPC...

Page 8: ...dentification Register bit assignments 3 20 Figure 3 9 PrimeCell Identification Register bit assignments 3 22 Figure 4 1 IPCMTCR Register bit assignments 4 3 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 9: ...rocessor Communications Module PL320 Technical Reference Manual TRM It contains the following sections About this manual on page x Feedback on page xiv Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 10: ...d into the following chapters Chapter 1 Introduction Read this chapter for an introduction to the IPCM and its features Chapter 2 Functional Overview Read this chapter for a description of the major functional blocks of the IPCM Chapter 3 Programmer s Model Read this chapter for a description of the IPCM registers and programming details Chapter 4 Programmer s Model for Test Read this chapter for ...

Page 11: ... monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value monospace bold Denotes language keywords when used outside example code and Angle brackets enclose replaceable terms for assembler syntax where they appear in code or code fragments They appear in normal font in running text For example MRC p15 0 Rd CRn CRm Opcode_2 The Opcode_2 value sel...

Page 12: ...sponse channel signals Prefix C Denotes AXI low power interface signals Prefix H Denotes Advanced High performance Bus AHB signals Prefix n Denotes active LOW signals except in the case of AXI AHB or Advanced Peripheral Bus APB reset signals Prefix P Denotes APB signals Prefix R Denotes AXI read channel signals Prefix W Denotes AXI write channel signals Suffix n Denotes AXI AHB and APB reset signa...

Page 13: ...ntains information that is specific to the IPCM Refer to the following documents for other relevant information AMBA Specification Rev 2 0 ARM IHI 0011 AMBA AXI Protocol Specification ARM IHI 0022 DSP Integration Specification ARM IHI 0026 Message Passing Software Integration Guide ARM DII 0091 PrimeCell Inter Processor Communications Module Implementation Guide ARM DII 0107 PrimeCell Inter Proces...

Page 14: ...email to errata arm com giving the title the number the relevant page number s to which your comments apply a concise explanation of your comments ARM Limited also welcomes general suggestions for additions and improvements Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arro...

Page 15: ...e IPCM on page 1 2 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from A...

Page 16: ...ster with separate Set Clear and Status addresses to enable you to mask out individual mailbox interrupts for cores requiring to poll rather than be interrupted a single 2 bit Mailbox Send Register to trigger mailbox interrupts to source and destination cores 0 7 32 bit data registers to store the message 1 32 sets of read only interrupt status registers one for each interrupt each comprising 1 32...

Page 17: ...s source destination mode and mask enable the configured IPCM to be used by different cores in different ways depending on the current application Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arr...

Page 18: ...om Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 19: ...2 18 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downl...

Page 20: ...integration of the IPCM in a multiprocessing system AHB interface SCANENABLE SCANINHCLK SCANOUTHCLK IPCMINT 31 0 Mailboxes and control logic Interrupt generation logic HCLK HRESETn HADDR 11 2 HREADY HSEL HWRITE HSIZE 2 0 HWDATA 31 0 HRDATA 31 0 HREADYOUT HRESP 1 0 IPCM MBOXNUM 5 0 INTNUM 5 0 DATANUM 2 0 HTRANS Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded...

Page 21: ...INT 0 IPCMINT 1 IPCMINT 2 Shared AHB COREID 0x00 COREID 0x01 COREID 0x02 Local AHB Local AHB IPCMINT 31 0 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Download...

Page 22: ...errupt lines and therefore handled by different ISRs A multi core system normally has at least one IPCM instantiated More can be instantiated if required Because the IPCM is configurable you can have several differently configured IPCMs instantiated in the same system The operation of the IPCM is described in more detail in the following sections Basic operation Channel ID on page 2 5 Using mailbo...

Page 23: ...n the mailbox to send another message or release the mailbox freeing it up for other cores in the system to use it 2 2 2 Channel ID The Channel ID is defined as the one hot encoded value that corresponds to a specific interrupt output from the IPCM An IPCM configured to have 32 interrupt outputs has 32 corresponding Channel IDs The Channel ID programs the Mailbox Source Mailbox Destination and Mai...

Page 24: ... 16 0x00020000 IPCMINT 17 0x00040000 IPCMINT 18 0x00080000 IPCMINT 19 0x00100000 IPCMINT 20 0x00200000 IPCMINT 21 0x00400000 IPCMINT 22 0x00800000 IPCMINT 23 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Download...

Page 25: ...12 Usage constraints on page 2 16 0x01000000 IPCMINT 24 0x02000000 IPCMINT 25 0x04000000 IPCMINT 26 0x08000000 IPCMINT 27 0x10000000 IPCMINT 28 0x20000000 IPCMINT 29 0x40000000 IPCMINT 30 0x80000000 IPCMINT 31 Table 2 1 Channel ID to interrupt mapping continued Channel ID Interrupt output Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downlo...

Page 26: ...ngle bit in the Mailbox Destination Register by writing that bit to the Destination Clear Register When the source core defines the mode of a mailbox it defines which other cores are to receive the message by programming the OR of all the Channel IDs into the Mailbox Destination Register If a core has more than one Channel ID only one is used per message You can only write to the Mailbox Destinati...

Page 27: ...pt Destination cores must clear their interrupts by writing their Channel ID value to the Destination Clear location This clears their Channel ID from the Mailbox Destination Register When the Mailbox Destination Register finally reaches zero indicating that all destination cores have cleared their interrupts the mailbox automatically detects this clears bit 0 and sets bit 1 of the Mailbox Send Re...

Page 28: ...ailbox2 to enable the acknowledge interrupt to be sent back to the source core When Auto Link is disabled the source core is interrupted if an acknowledge interrupt is sent that has no effect on any other mailbox Note When using Auto Link with Auto Acknowledge the mailbox automatically sets Mailbox Send Register bit 1 in the first mailbox to send the acknowledge back to the source core but because...

Page 29: ...ta0 Send Data6 Mailbox31 IPCMMIS31 31 IPCMMIS0 31 31 Source 0 31 Destination 0 31 Mask 0 Mode Data0 Send Data6 Mailbox0 IPCMMIS31 0 IPCMMIS0 0 IPCMINT 31 IPCMINT 0 IPCMMIS31 31 0 IPCMMIS0 31 0 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

Page 30: ...e IPCM configuration tie off the MBOXNUM INTNUM and DATANUM input pins as follows Number of mailboxes Program the number of active mailboxes by tying off the MBOXNUM input bus Table 2 2 Table 2 2 Configuring number of mailboxes Number of mailboxes MBOXNUM 1 6 b000001 2 6 b000010 3 6 b000011 4 6 b000100 5 6 b000101 6 6 b000110 7 6 b000111 8 6 b001000 9 6 b001001 Downloaded from Arrow com Downloaded...

Page 31: ... Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

Page 32: ...from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

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Page 34: ...e updated When Auto Acknowledge is disabled the destination core must clear its interrupt by clearing bit 0 of the Mailbox Send Register Table 2 4 Configuring number of data registers Number of mailboxes DATANUM 0 3 b000 1 3 b001 2 3 b010 3 3 b011 4 3 b100 5 3 b101 6 3 b110 7 3 b111 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded f...

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Page 36: ...ge 2 19 shows the messaging sequence Core0 Interrupt controller0 Core1 Interrupt controller1 IPCM Minimum configuration MBOXNUM 4 INTNUM 2 DATANUM 1 IPCMINT 0 IPCMINT 1 IPCMINT 31 0 AHB bus Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Do...

Page 37: ...ly Mailbox0 is indicated 11 Core0 reads the Acknowledge payload data IPCM0SOURCE 1 0 IPCM0DSTATUS 1 0 IPCM0MODE IPCM0MSTATUS 1 0 IPCM0SEND 1 0 IPCM0DR0 31 0 IPCMRIS0 3 0 IPCMRIS1 3 0 IPCMINT 3 0 0 0 00000000 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 0 0 3 1 0 0 2 1 2 0 2 1 0 1 0 1 0 DA7A0000 DA7A1111 00000000 15 0 0 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downl...

Page 38: ...to back messaging from Core0 to Core1 Figure 2 8 on page 2 21 shows the messaging sequence Core0 Interrupt controller0 Core1 Interrupt controller1 IPCM Minimum configuration MBOXNUM 4 INTNUM 2 DATANUM 1 IPCMINT 0 IPCMINT 1 IPCMINT 31 0 AHB bus Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 39: ... IPCM0SOURCE 1 0 IPCM0DSTATUS 1 0 IPCM0MODE 1 0 IPCM0MSTATUS 1 0 IPCM0SEND 1 0 IPCM0DR0 31 0 IPCMRIS0 3 0 IPCMRIS1 3 0 IPCMINT 3 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 0 00000000 0 0 0 0 0 3 1 0 0 2 1 2 1 2 1 2 1 0 1 0 DA7A0000 DA7A1111 00000000 2 0 DA7A2222 DA7A3333 1 0 1 0 1 0 0 0 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 40: ...cknowledge Figure 2 10 on page 2 23 shows the messaging sequence Core2 Interrupt controller2 Core3 Interrupt controller3 IPCM Minimum configuration MBOXNUM 1 INTNUM 4 DATANUM 1 IPCMINT 2 IPCMINT 3 IPCMINT 31 0 Core0 Interrupt controller0 Core1 Interrupt controller1 IPCMINT 0 IPCMINT 1 AHB bus Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Do...

Page 41: ...31 0 IPCMRIS0 3 0 IPCMRIS1 3 0 IPCMINT 3 0 0 0 00000000 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 0 0 F 1 0 0 E 1 E C 4 1 0 DA7A0000 00000000 15 2 0 1 0 1 0 IPCMRIS2 3 0 0 1 0 IPCMRIS3 3 0 0 1 0 C 4 0 1 0 0 16 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloade...

Page 42: ...to Core1 Core1 responds to each interrupt separately and acknowledges both Core0 only obtains an acknowledge interrupt when Core1 has finished with the final message This example assumes that the IPCM has interrupts enabled and is not in integration test mode Mailboxes 2 3 are inactive and Auto Acknowledge is disabled Figure 2 11 on page 2 25 shows the configuration Downloaded from Arrow com Downl...

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Page 44: ...lly sent triggered by bit 1 in the IPCM0SEND Register going HIGH and Auto Link mode being active 14 Core1 reads the IPCMRIS1 Register and reads the data payload in Mailbox1 15 Core1 clears bit 0 and sets bit 1 in the IPCM1SEND Register to provide the Manual Acknowledge back to Core0 Note This sends the acknowledge interrupt to Core0 Downloaded from Arrow com Downloaded from Arrow com Downloaded fr...

Page 45: ...row com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Do...

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Page 48: ... of the IPCMxSOURCE IPCMxDCLEAR IPCMxDSET IPCMxDSTATUS IPCMxMCLEAR IPCMxMSET and IPCMxMSTATUS Registers For example when INTNUM is set to 1 the registers listed above are all only a single bit wide bit0 Setting INTNUM to 32 sets the registers to 32 bits wide Secondly INTNUM defines which IPCMRISx and IPCMMISx registers are available For example when INTNUM is set to 1 only the IPCMRIS0 and IPCMMIS...

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Page 50: ...0 Peripheral Identification Register 1 Peripheral Identification Register 2 Peripheral Identification Register 3 PrimeCell Identification Register 0 PrimeCell Identification Register 1 PrimeCell Identification Register 2 PrimeCell Identification Register 3 0x000 0x040 0x080 0x0C0 0x100 0x140 0x180 0x1C0 0x200 0x240 0x280 0x2C0 0x300 0x340 0x380 0x3C0 0x400 0x440 0x480 0x4C0 0x500 0x540 0x580 0x5C0...

Page 51: ...m Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Download...

Page 52: ...sters on page 3 17 IPCM0DR6 0x03C RW 0x00000000 See Mailbox Data Registers on page 3 17 0x040 0x0 7C Reserved for Mailbox1 0x080 0x0 BC Reserved for Mailbox2 0x0C0 0x0 FC Reserved for Mailbox3 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

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Page 54: ... Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloade...

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Page 58: ...it Name Function 31 0 Destination Set Used to set bits in the IPCMxDSTATUS Registers Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Dow...

Page 59: ... Registers Table 3 5 IPCMxDSTATUS Register bit assignments Bit Name Function 31 0 Destination Status Gives the status of the Mailbox Destination Register Defines which interrupt output to assert for the message Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloa...

Page 60: ...te as zero 1 Auto Link Set to enable Auto Link 0 Auto Acknowledge Set to enable Auto Acknowledge Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from A...

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