Programmer’s Model
ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
3-23
PrimeCell Identification Register 1
The hard-coded IPCMPCellID1 Register defines the reset value. Table 3-20 lists the bit
assignments for the IPCMPCellID1 Register.
PrimeCell Identification Register 2
The hard-coded IPCMPCellID2 Register defines the reset value. Table 3-21 lists the bit
assignments for the IPCMPCellID2 Register.
PrimeCell Identification Register 3
The hard-coded IPCMPCellID3 Register defines the reset value. Table 3-22 lists the bit
assignments for the IPCMPCellID3 Register.
Table 3-20 IPCMPCellID1 Register bit assignments
Bits
Name
Description
[31:8]
-
Read undefined
[7:0]
IPCMPCellID1
These bits read back as
0xF0
Table 3-21 IPCMPCellID2 Register bit assignments
Bits
Name
Description
[31:8]
-
Read undefined
[7:0]
IPCMPCellID2
These bits read back as
0x05
Table 3-22 IPCMPCellID3 Register bit assignments
Bits
Name
Description
[31:8]
-
Read undefined
[7:0]
IPCMPCellID3
These bits read back as
0xB1
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