ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
v
List of Tables
PrimeCell Inter-Processor Communications
Module (PL320) Technical Reference Manual
Change history .............................................................................................................. ii
Table 2-1
Channel ID to interrupt mapping ............................................................................... 2-6
Table 2-2
Configuring number of mailboxes ........................................................................... 2-12
Table 2-3
Configuring number of interrupts ............................................................................. 2-14
Table 2-4
Configuring number of data registers ...................................................................... 2-16
Table 3-1
IPCM register summary ............................................................................................ 3-6
Table 3-2
IPCMxSOURCE Register bit assignments .............................................................. 3-12
Table 3-3
IPCMxDSET Register bit assignments ................................................................... 3-12
Table 3-4
IPCMxDCLEAR Register bit assignments ............................................................... 3-13
Table 3-5
IPCMxDSTATUS Register bit assignments ............................................................ 3-13
Table 3-6
IPCMxMODE Register bit assignments .................................................................. 3-14
Table 3-7
IPCMxMSET Register bit assignments ................................................................... 3-15
Table 3-8
IPCMxMCLEAR Register bit assignments .............................................................. 3-15
Table 3-9
IPCMxMSTATUS Register bit assignments ............................................................ 3-16
Table 3-10
IPCMxSEND Register bit assignments ................................................................... 3-17
Table 3-11
IPCMxDR0-6 Register bit assignments ................................................................... 3-17
Table 3-12
IPCMMISx Register bit assignments ....................................................................... 3-18
Table 3-13
IPCMRISx Register bit assignments ....................................................................... 3-18
Table 3-14
IPCMCFGSTAT Register bit assignments .............................................................. 3-19
Table 3-15
IPCMPeriphID0 Register bit assignments ............................................................... 3-20
Table 3-16
IPCMPeriphID1 Register bit assignments ............................................................... 3-21
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