ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
Index-1
Index
A
AHB interface 2-2
AHB slave signals A-2
B
Block diagram 2-2
C
Channel ID 2-5
Configurable parameters 1-3
Control logic 2-2
Conventions
numerical xiii
signal naming xii
timing diagram xi
typographical xi
Customization
number of data registers 2-16
number of interrupts 2-14
D
DATANUM
A-3
F
Features 1-2
G
Global signals A-2
H
HADDR
A-2
HCLK
A-2
HRDATA
A-2
HREADY
A-2
HREADYOUT
A-2
HRESETn
A-2
HRESP
A-2
HSEL
A-2
HSIZE
A-2
HTRANS
A-2
HWDATA
A-2
HWRITE
A-2
I
Interrupt generation logic 2-2
INTNUM
A-3
IPCM signals A-3
IPCMCFGSTAT Register 3-18
IPCMINT
A-3
IPCMMISx Registers 3-17
IPCMPCellD0 Register 3-22
IPCMPCellD0-3 Registers 3-22
IPCMPCellD1 Register 3-23
IPCMPCellD2 Register 3-23
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