Programmer’s Model
3-18
Copyright © 2003, 2004. ARM Limited. All rights reserved.
ARM DDI 0306B
Figure 3-6 Mailbox status
The Masked Interrupt Status Registers identify which mailbox triggered the interrupt.
This value is the logical AND of the raw interrupt status with the Mailbox Mask Status
Registers. All Masked Interrupt Status Register outputs are ORed together to form the
IPCMINT[31:0]
interrupt output bus.
Table 3-12 lists the register bit assignments.
3.3.12
Raw Interrupt Status Registers
The read-only IPCMRISx Registers indicate the unmasked interrupt status of each
mailbox for each core.
Table 3-13 lists the register bit assignments.
3.3.13
Configuration Status Register
The read-only IPCMCFGSTAT Register indicates the hardware configuration options
chosen for implementation of the IPCM.
Figure 3-7 on page 3-19 shows the register bit assignments.
IPCM0MASK[0]
IPCM0SEND[0]
IPCM0DEST[0]
IPCM0SEND[1]
IPCM0SOURCE[0]
IPCMMIS0[0]
IPCMRIS0[0]
Table 3-12 IPCMMISx Register bit assignments
Bit
Name
Function
[31:0]
MaskIntStat
Masked interrupt status
Table 3-13 IPCMRISx Register bit assignments
Bit
Name
Function
[31:0]
RawIntStat
Raw interrupt status
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