Functional Overview
2-22
Copyright © 2003, 2004. ARM Limited. All rights reserved.
ARM DDI 0306B
12.
Core1 reads the IPCMRIS1 Register and reads the data payload.
13.
Core1 optionally updates the data payload for the Acknowledge,
DA7A3333
.
14.
Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to provide the
Manual Acknowledge back to Core0.
15.
Core0 reads the IPCMRIS0 Register and reads the data payload.
16.
Core0 clears the interrupt and releases ownership of the mailbox by clearing the
IPCM0SOURCE Register, which in turn clears the IPCM0DSTATUS,
IPCM0MSTATUS, IPCM0SEND, and IPCM0DR0 Registers.
2.3.3
Messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge
In this example system, there are four cores and four mailboxes:
•
Core0 uses Channel ID1
•
Core1 uses Channel ID2
•
Core2 uses Channel ID4
•
Core3 uses Channel ID8.
Core0 is the source core and sends a message to three destination cores, 1, 2, and 3. This
example assumes that the IPCM is not in integration test mode. Mailboxes 1-3 are
inactive and Auto Link is disabled. Figure 2-9 shows the configuration.
Figure 2-9 Configuration, messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge
Figure 2-10 on page 2-23 shows the messaging sequence.
Core2
Interrupt
controller2
Core3
Interrupt
controller3
IPCM
Minimum
conf iguration:
M BOXNUM
=1
INTNUM
=4
DATANUM
=1
IPCM INT[2]
IPCM INT[3]
IPCM INT[31:0]
Core0
Interrupt
controller0
Core1
Interrupt
controller1
IPCM INT[0]
IPCM INT[1]
A HB bus
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