Functional Overview
ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
2-7
Note
The configured number of interrupt outputs defines the width of the Channel ID.
In a system that has one IPCM interrupt per core, each core has a single Channel ID that
defines it within the IPCM. Some systems can have multiple IPCM interrupts per core,
and therefore multiple Channel IDs per core.
2.2.3
Using mailboxes
This section describes:
•
Defining source core
on page 2-8
•
Defining destination core
on page 2-8
•
Using the Mailbox Mask Register
on page 2-8
•
Using the Mailbox Send Register
on page 2-9
•
Mailbox Data Registers
on page 2-9
•
Setting mode
on page 2-9
•
Interrupts and status Registers
on page 2-10
•
Configuration Status Register
on page 2-12
•
Usage constraints
on page 2-16.
0x01000000
IPCMINT[24]
0x02000000
IPCMINT[25]
0x04000000
IPCMINT[26]
0x08000000
IPCMINT[27]
0x10000000
IPCMINT[28]
0x20000000
IPCMINT[29]
0x40000000
IPCMINT[30]
0x80000000
IPCMINT[31]
Table 2-1 Channel ID to interrupt mapping (continued)
Channel ID
Interrupt output
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