UG-1828
Preliminary Technical Data
Rev. PrC | Page 70 of 338
MICROPROCESSOR AND SYSTEM CONTROL
ADRV9001 supports quick configuration from idle states of operation and quick transition between receive and transmit states. Those
transitions are handled by internal blocks called stream processors. Stream processor is a processor within the ADRV9001 device assigned
to perform a series of configuration tasks upon an external request. Upon a request from the user, the stream processor performs a series
of actions defined in the image loaded into the ADRV9001 during initialization process.
The stream processor therefore has streams (series of tasks) for:
•
Tx1 Enable/Tx1 disable
•
Tx2 Enable/Tx2 disable
•
Rx1 Enable/Rx1 disable
•
Rx2 Enable/Rx2 disable
Enabling and disabling paths is done typically using pins, however can also be controlled over the SPI bus using API command. The
stream is not limited to path enabling events and can react to other events such as a DGPIO input signal.
ADRV9001 is flexible in its configuration, and therefore, the stream is flexible. In the same way as the initialization structures change with
profile, so the stream processor image must change with configuration, for example, the stream that enables Rx1 differs depending on
whether a narrowband or a wideband setup is chosen. For this reason, it is necessary to use a stream image for each configuration of the
device. In this way, when the user saves configuration files (.c) using the ADRV9001 TES, a stream image is also saved automatically. This
stream file should then be used when using these configuration files.
Figure 61 describes the general ecosystem of ADRV9001. On the right-hand side (data side), ADRV9001 interfaces with the BBIC and on
the left-hand side (antenna side), it interfaces with the RF components. The following section describes control of the ADRV9001
datapaths.
Figure 61. Datapath Control Signals
Rx1 DATA PATH
Rx1 SSI
LNA
Rx2 DATA PATH
Rx2 SSI
LNA
Tx1 DATA PATH
Tx1 SSI
PA
Tx2 DATA PATH
Rx1
STREAM
PROC.
Rx2
STREAM
PROC.
Tx1
STREAM
PROC.
Tx2
STREAM
PROC.
PA
RAMP
CONTROL
SPI
INTERFACE
Tx2 SSI
LNA1_CTRL
LNA2_CTRL
RF_SWITCH1
RF_SWITCH2
PA1_BIAS
PA2_BIAS
Rx1_ENABLE
Rx2_ENABLE
Tx1_ENABLE
Tx2_ENABLE
RAMP1_EN
RAMP2_EN
SPI INTERFACE
PA
SWITCH
SWITCH
AuxDAC1
AuxDAC1
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