UG-1828
Preliminary Technical Data
Rev. PrC | Page 86 of 338
CLOCK GENERATION
CLOCK GENERATION
In ADRV9001 all clocks for the converters and main digital are generated by CLKGEN. CLKGEN receives from two clocks, a high
performance (HP) clock PLL and a low power (LP) PLL. The high performance clock PLL has a programmable frequency range of
7.2 GHz to 8.8 GHz. The low power clock PLL can generate a programmable range of 3.3 GHz to 5 GHz frequency. CLKGEN also has the
clocks be divided and retimed with reset pulses from the clock PLLs.
Figure 79. ADRV9001 Clock Generation
Figure 80. CLKPLL Can Be Programmed to Provide Arbitrary Clock Speed
Low Power Clock PLL (LP CLKPLL)
By default, LP CLKPLL works at a fixed frequency at 4423.68 MHz. However, the user can set it to have a tuning operation range. The
operating frequency range of LP CLKPLL is from 3.3 GHz to 5 GHz. User only must provide their final sampling frequency at the
interface, and the final frequency of LP CLKPLL are determined internally. This is all done before the chip is programmed. A profile is
generated based on the user’s provided sampling frequency.
Note LP CLKPLL uses less power than HP CLKPLL but produces more jitter noise. User must take this trade-off into consideration for
their end application. Note that, in most profiles, LP CLKPLL meets the performance requirements.
Table 30 lists the supported data sample rate with different standards by LP CLKPLL. Table 31 lists the supported data lane rate by LP
CLKPLL. Note the LTE 40 MHz at 16-bit is not supported by the LP CLKPLL.
Table 30. Sample Rate Supported By LP CLKPLL
Standard
Sample Rate
DMR I/Q
2.40E + 04
TETRA
1.44E + 05
TETRA
2.88E + 05
LTE 1.5
1.92E + 06
LTE 3
3.84E + 06
LTE 5
7.68E + 06
LTE 10
1.54E + 07
LTE 15
2.30E + 07
LTE 20
3.07E + 07
LTE 40 @12 bits
6.14E + 07
Table 31. Supported Data Lane Rate By LP CLKPLL
Standard
Serialization Factor Per Data Lane
Data Lane Rate
DMR/P25 Direct Modulation
2
9.60E +03
P25 Direct Modulation
2
1.20E +04
FM Direct Modulation
16
1.28E +05
DMR I/Q
32
7.68E + 05
8
1.92E + 05
16
3.84E + 05
CLK PLL AND
PHASE SYNC
7200 TO
8847.36MHz
CLK GEN
TO MAIN
DIGITAL
/1,/2,/3,/4
/2 TO /31
/2 TO /31
/2 TO /31
LPCLK PLL AND
PHASE SYNC
3300 TO
5000MHz
24159-
070
CONFIGURABLE
DECIMATORS
HP BBPLL
8.8G TO 7.2G
HP BBPLL
3.3G TO 5G
DESIRED
SAMPLE RATE
HP ADC
LP ADC
/4
/12
/8
/6
24159-
071
