Preliminary Technical Data
UG-1828
Rev. PrC | Page 269 of 338
POWER SUPPLY RECOMMENDATIONS
Aim of this chapter is to provide reader with an overview of ADRV9001 power supply solution. Power supply solution for ADRV9001 will
change based on user desired mode of operation (FDD, TDD, DPD, Tx tracking, number of active Rx inputs, number of active Tx
outputs, internal LOs vs external LOs, 1.0V power domain) therefore it is important to understand available configurations and optimize
PCB layout based on selected mode. Power supply solution implements on an EVB will be used as a reference in this chapter.
POWER MANAGEMENT CONSIDERATIONS
The ADRV9001 family of devices requires four or five different power supply domains:
(1)
1.0V Digital: this supply is connected to the device through the two VDIG_1P0 pins. This is the supply that feeds all digital
blocks. Care should be taken to properly isolate this supply from all analog signals on the PCB to avoid noise corruption. This
supply input can have a tolerance of ±5%, but note that the total tolerance must include the tolerance of the supply device added
to the voltage drop of the PCB. In some modes of operation, this supply can draw high current. It is critical that the input traces
for these two inputs be balance (same impedance for inputs) and as thick as possible to minimize the I×R drop.
(2)
1.0V Analog: these supplies are collectively referred to in the datasheet as the VDDA_1P0 supply. This power domain is
optional and suggested to be used only in scenario where minimum power consumption is to be achieved. It will require low
noise 1.0V power domain available in the end system. In mode of operation where VDDA_1P0 is not used, this 1.0V power
domain is created internally inside the ADRV9001 by its own LDOs. This power domain, supplies voltage to noise sensitive
blocks of the ADRV9001. If user intend to provide external 1.0V, care should be taken to ensure very low noise level on this
power domain. This supply input has a tolerance of ±2.5%.
(3)
1.3V Analog: these supplies connect to all functional blocks in the device through number of different input pins. They are
collectively referred to in the datasheet as the VDDA_1P3 supply. Each input should be treated as a noise-susceptible input,
meaning proper decoupling and isolation techniques should be followed to avoid crosstalk between channels. The tolerance on
these supply inputs is ±2.5%. If VDDA_1P0 is utilized, some of VDDA_1P3 supply pins will change its intended voltage input
level from 1.3V to 1.0V. This chapters provides detail overview of those modifications.
(4)
1.8V Analog: these supplies are primarily used to supply the transmitter outputs. They also supply current for multiple
transmitter, receiver, converter, and auxiliary converter blocks. They are collectively referred to in the datasheet as the
VDDA_1P8 supply. This supply has a tolerance of ±5%.
(5)
1.8V Digital: This is an interface supply. The VDIGIO_1P8 supply is a separate power domain shared with the BBP interface.
The nominal input voltage on this supply is 1.8V with a tolerance of ±5%. This input serves as the voltage reference for the
digital interface (SPI and SSI), DGPIO, and digital control inputs.
IMPORTANT:
During operation, supply currents can vary significantly, especially if operating in TDD mode. The supply needs to have adequate
capacity to provide the necessary current (as indicated on the datasheet) so that performance criteria over all process and
temperature variations are maintained. ADI recommends adding at least 15% margin to all supply maximums to ensure proper
operation under all conditions.
POWER SUPPLY SEQUENCE
The ADRV9001 requires a specific power-up sequence to avoid undesired power-up currents. The optimal power-on sequence requires
VDD_1P0 to power up first. The VDDA_1P3, VDDA_1P8 and VDD_1P8 supplies must then power up after the VDD_1P0 supply. If
VDDA_1P0 is utilized, it must be powered up after VDDA_1P3 and VDDA_1P8 are enabled. The user must toggle the RESET signal
after power has stabilized prior to configuration.
The power-down sequence recommendation is similar to power-up. All supplies should be disabled in any order (or all together) before
VDIG_1P0 is disabled. If such a sequence is not possible, then all supplies should have their sources disabled simultaneously to ensure
there is no back feeding circuits that have not been powered down.
