Preliminary Technical Data
UG-1828
Rev. PrC | Page 193 of 338
Figure 178 shows TX/RX Enable pin powers up/down channels. If Tx/Rx Enable Pin power down mode is set to mode 1, TX1/RX1
Enable falling edge powers down TX1/RX1 PLL and TX1/RX1 datapath, rising edge powers them up. As mentioned previously, the
higher power down mode, the longer recovery time, users should make sure their system has enough transition time between the power
down and power up of the same component if users set a high power down mode. For example: if TX1 and RX1 uses the same internal
PLL and there is very short transition time between TX enable falling edge and RX enable rising edge, then mode 1 and 2 should not be
selected because the same PLL and LDOs are always used.
Figure 178. TX/RX Enable Pin triggers Power Saving
DGPIO Triggers Power Saving
DGPIO pin triggered Channel Power Saving can provide additional power saving than the TX/RX Enable pin when it is enabled,
therefore if enabled, the power down mode triggered by DGPIO should be larger than TX/RX enable pin triggered power down mode.
Both TX and RX channel would be powered down at the DGPIO rising edge and powered up at the DGPIO falling edge, this is because
only one DGPIO is assigned for TX and RX channel. Users should be noticed, the DGPIO can only be allowed to pull up when both TX
Enable and Rx Enable is low.
Figure 179. TX/RX Pin Triggers Power Saving and DGPIO Triggers Power-Down Saving
Figure 179 shows an example that both TX/RX enable and DGPIO pin trigger power saving is enabled. The grey time slots are the ones
TX/RX must be active. If TX and RX transition time is not long enough to allow power down mode 1 or 2, then users have to select
TX/RX Enable pin power down mode to 0. DGPIO power saving can be engaged during time slots 2 and 3 by selecting power down
mode 2 to power down both TX/RX LDOs and PLLs in slot 2 and slot 3 areas which neither TX nor RX is active.
The API command adi_adrv9001_powerSavingAndMonitorMode_ChannelPowerSaving_Configure () is used to configure Channel
Power Saving modes for a specified channel. It can be called in Calibrated, Primed or RF Enabled state. The new setting would not take
effect immediately after mailbox acknowledgment but start at the power down pin edge (Enable falling edge and DGPIO rising
edge). Baseband processor should leave enough time to send this command and receive acknowledge before the next power down event.
The channel power saving trigger modes are defined in following data structure:
typedef struct adi_adrv9001_PowerSavingAndMonitorMode_ChannelPowerSavingCfg
{
adi_adrv9001_PowerSavingAndMonitorMode_ChannelPowerDownMode_e channelDisabledPowerDownMode;
adi_adrv9001_PowerSavingAndMonitorMode_ChannelPowerDownMode_e gpioPinPowerDownMode;
} adi_adrv9001_PowerSavingAndMonitorMode_ChannelPowerSavingCfg_t;
The enumerator adi_adrv9001_PowerSavingAndMonitorMode_ChannelPowerDownMode defines three power down modes that has
been described in .
TX1 ENABLE
TX ENABLE OFF
POWERING DOWN
COMPONENTS BASED ON
POWER SAVING MODE
TX ENABLE ON
POWERING ON
COMPONENTS BASED ON
POWER SAVING MODE
RX ENABLE OFF
POWERING DOWN
COMPONENTS BASED ON
POWER SAVING MODE
RX ENABLE ON
POWERING ON
COMPONENTS BASED ON
POWER SAVING MODE
RX1 ENABLE
TRX1
TX ON
RX ON
TX ON
24159-
136
CH1
1
TX
time slots
RX Enable
2
3
4
RX
1
TX
2
3
4
RX
time slots
GPIO
TX Enable
