Analog Devices ADRV9001, User Manual

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UG-1828 Preliminary Technical Data
Rev. PrC | Page 66 of 338
adi_adrv9001_SsiDataFormat_e ssiDataFormatSel;
adi_adrv9001_SsiNumLane_e numLaneSel;
adi_adrv9001_SsiStrobeType_e strobeType;
uint8_t lsbFirst;
uint8_t qFirst;
adi_adrv9001_SsiTxRefClockPin_e txRefClockPin;
bool lvdsIBitInversion;
bool lvdsQBitInversion;
bool lvdsStrobeBitInversion;
uint8_t lvdsUseLsbIn12bitMode;
bool lvdsRxClkInversionEn;
bool cmosDdrPosClkEn;
bool cmosClkInversionEn;
bool DdrEn;
bool rxMaskStrobeEn;
} adi_adrv9001_SsiConfig_t;
In the data structure, the previously mentioned SSI modes are defined for each Tx/RX channel, Table 20 lists the SSI configuration
parameters and some default values, users can find the detail data structure and enumerator description in API Doxygen help file.
Table 20 SSI Configuration Parameters
Parameter Type Description Note
ssiType enum Sets SSI type
ssiDataFormatSel enum Set SSI data format
numLaneSel enum Set SSI number of lanes
strobeType enum Set SSI strobe type
lsbFirst uint8_t Set LSB first Default ‘0’, MSB first
qFirst uint8_t Set Q data first Default ‘0’, I data first
txRefClockPin enum Set TX SSI reference clock output (TX_DCLK_OUT) options
lvdsIBitInversion bool Set LVDS SSI I bit differential pads polarity inversion Default ‘false’
lvdsQBitInversion bool Set LVDS SSI Q bit inversion Default ‘false’’, Rx SSI
ignores this field, I/Q
lanes share the
configuration of
“lvdsIBitInversion”
lvdsStrobeBitInversion bool Set LVDS SSI strobe bit inversion Default ‘false’’
lvdsUseLsbIn12bitMode uint8_t Set LVDS 12 bit mode Default ‘0’, LVDS SSI uses
16 bit mode
lvdsRxClkInversionEn bool Set LVDS RX SSI clock inversion enable Default ‘false’
cmosDdrPosClkEn bool Set CMOS DDR positive clock enable Default ‘false’
cmosClkInversionEn bool Set CMOS DDR clock inversion enable Default ‘false’
DdrEn bool Set DDR mode enable
rxMaskStrobeEn bool Set Rx Strobe Mask, mask the Rx SSI Strobe when
interface rate is multi times of sample rate, refer Figure 36 Default ‘false’
Figure 44 illustrates the Rx CMOS SSI interface with DDR clock in relation with strobe/data. To make sure the BBIC can get the best
setup/hold timing margin for RX CMOS DDR SSI, with Table 20 RX CMOS DDR relative default SSI configurations
(cmosDdrPosClkEn=false, cmosClkInversionEn=false), the Rx CMOS SSI output clock/strobe/data phase timing diagram is shown in
Figure 56. We would recommend users using this default RX CMOS SSI DDR configuration.