UG-1828
Preliminary Technical Data
Rev. PrC | Page 276 of 338
POWER SUPPLY CONFIGURATIONS
From power supply implementation point of view, the ADRV9001 can work in multiple configurations. This section outlines them in
details. Depends on final application of ADRV9001 in end system user have a freedom to implement different ways to power the IC. Final
solution will depend on:
1.
if external 1.0V power domain is utilized or not
2.
type of application: FDD, TDD
a.
In FDD case if DPD and/or Tx tracking calibrations are utilized or not
3.
number of active Rx inputs and number of active Tx outputs,
a.
Note should be taken that in scenario where Rx2/Tx2 are used and Rx1/Tx1 are not used (not recommended scenario
from an optimal power savings point of view) the power supply to VANA1_1P3 (C8) needs to be present.
4.
LO scheme:
a.
Internal LOs with internal PLL+VCO+LO_GEN powered by internal LDO
b.
External LOs with internal LO_GEN powered by
i.
internal LDO
ii.
external LDO
Note should be taken that even in scenarios when external LO are utilized the VRFVCO1_1P0 (B9), VRFVC01_1P3
(A10) and VRFSYN1_1P3 (E11) needs to be powered up. The RF PLL1 is used to generate test signals during
initialization calibration stage therefore power supply to those blocks needs to be provided. After initial calibrations
are performed those blocks are powered down internally.
This section will outline how decisions based on descriptions above could impact final power supply interconnectivity.
Figure 263 outlines recommended power supply interconnective in scenarios where user might want to utilize external 1.0V analog power
domain. In such mode number of power supply input pins that are assigned to 1.3V analog power domain will have to be re-connected
physically on PCB to new 1.0V analog power domain. In case where external RF LO is used, more power savings can be achieved by
physically disconnecting/grounding LO supplies responsible for powering up internal LO generation blocks.
Figure 265 and Figure 264 provides user with recommendations how to interconnect power supply in case where not all of available RF
IOs (Tx and Rx) are utilized in end application. It should be noted that in order to perform Tx1 tracking calibration or DPD on Tx1, Rx1
data path must to be available to observe Tx output. The same relationship exists between Tx2 and Rx2. It is not possible to perform Tx1
tracking calibration or DPD operation on Tx1 output using Rx2 data path (and vice versa, Tx2 using Rx1).
Figure 265 provides suggestions for 1T1R configuration. In TDD applications, in order to achieve lowest possible current consumption in
deep sleep state user should utilize Rx1 and Tx1 data paths and disable Rx2 and Tx2 data paths.
Once any of configurations outlined in Figure 263, Figure 265 or Figure 264 is implemented, user needs to initialize ADRV9001 device
with correct initialization settings in described in data structure TBD.
