Preliminary Technical Data
UG-1828
Rev. PrC | Page 253 of 338
Figure 241. Trace Fan-Out Scheme on ADRV9001 Evaluation Card (PCB layer TOP and Layer 8 Enabled)
COMPONENT PLACEMENT AND ROUTING PRIORITIES
The ADRV9001 transceiver requires few external components to function, but those that are needed require careful placement and
routing to optimize performance. This section provides a priority order and checklist for properly placing and routing critical signals and
components as well as those whose location and isolation are not as critical.
Board layout design involves compromise. The recommendations within this User Guide are intended for wide RF bandwidth
applications. For narrow RF bandwidth applications, the board line impedance parameters within this document may not be optimal.
The following list provides general suggestions for board design:
•
Match the customer board design as close as possible to the ADRV9001 board design.
•
Be attentive to power distribution and power ground return methodology.
•
Do not run high speed digital lines in close proximity to dc power distribution routes or RF line routes.
Signals with Highest Routing Priority
RF lines and DEV_CLK clock are the signals that are most critical and should be routed with highest priority. Figure 242 shows the
general directions in which each of the signals should be routed so that they can be properly isolated from noisy signals.
4.5mil
TRACE
VIA-IN-THE-PAD
VIA SIZE = 14mil
PAD SIZE = 15mil
AIR GAP = 17.5mil
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290
