Analog Devices ADRV9001, User Manual

Page: 250 / 338

UG-1828 Preliminary Technical Data
Rev. PrC | Page 250 of 338
when ADRV9001 is intended to operate with LMR type standards. Ideally DEV_CLK phase noise requirement should be derived from
customer specific application and its requirements set for adjacent channel rejection.
In general, using a higher phase noise source can degrade performance delivered by ADRV9001 transceiver.
Table 103. DEV_CLK_IN Phase Noise Requirements for 1dB system PN degradation compared to an ideal DEVICE CLOCK
Frequency
Offset From
Carrier
Narrow PLL Loop Bandwidth (Approximately
50 kHz) (Default, Typically <3 GHz) Wide PLL Loop Bandwidth (Approximately 300 kHz)
(User Configured, Typically >3 GHz )
122.88 MHz
(dBc/Hz) 153.6 MHz
(dBc/Hz) 245.76 MHz
(dBc/Hz) 122.88 MHz
(dBc/Hz) 153.6 MHz
(dBc/Hz) 245.76 MHz
(dBc/Hz)
100 Hz −113.02 −111.08 −107.00 −114.02 −112.08 −108.00
1000 Hz −125.02 −123.08 −119.00 −127.02 −125.08 −121.00
10 kHz −133.02 −131.08 −127.00 −138.02 −136.08 −132.00
100 kHz −137.02 −135.08 −131.00 −146.02 −144.08 −140.00
1 MHz −133.02 −131.08 −127.00 −147.02 −145.08 −141.00
10 MHz −104.02 −102.08 −98.00 −118.02 −116.08 −112.00
Table 104. DEV_CLK_IN Phase Noise Requirements for LMR Type Applications
Frequency Offset From Carrier PLL Loop Bandwidth Optimized for LMR Type Applications, 38.4 MHz (dBc/Hz)
100 Hz −106
1000 Hz −151
10 kHz −151
100 kHz −151
10 MHz −151
CONNECTION FOR MULTICHIP SYNCHRONIZATION (MCS) INPUT
A LVDS type MCS signal applied between MCS+(D7) and MCS-(D8) pins is used to provide time alignment synchronization for the both
RF and datalink systems. Similar to device clock input signal, a clock source with fast rise and fall times should be used as MCS input
signal. PCB traces for routing MCS signals should be implemented following guidelines that are similar to LVDS mode device clock input
trace.